10AX115U3F45E2SG 鏅傞枔锛�2025/5/10 14:34:29 闁辫畝锛�28

10AX115U3F45E2SG 鏄竴娆剧敱鑻辩壒鐖撅紙Intel锛夋帹鍑虹殑 Stratix 10 绯诲垪 FPGA 鑺墖銆傝┎绯诲垪鍩轰簬 14nm 宸ヨ棟鎶€琛�(sh霉)鍒堕€�锛岄泦鎴愪簡澶ч噺鐨勯倧杓柈鍏�銆丏SP 妯″鍜屽祵鍏ュ紡瀛樺劜鍣ㄨ硣婧愶紝閬╁悎鐢ㄤ簬楂樻€ц兘瑷堢畻銆佺恫(w菐ng)绲�(lu貌)铏曠悊銆佷俊铏熻檿鐞嗕互鍙婂叾浠栧京(f霉)闆滅殑鎳�(y墨ng)鐢ㄥ牬鏅�銆�
銆€銆€Stratix 10 绯诲垪閲囩敤浜� Intel 鐨� HyperFlex 鏋舵(g貌u)锛屾棬鍦ㄦ彁鍗囨檪閻橀牷鐜囧拰鎬ц兘鏁堢巼銆傛澶栵紝閫欐 FPGA 鏀寔澶氱ó楂橀€熸帴鍙�锛屽寘鎷� PCIe銆佷互澶恫(w菐ng)鍜屾敹鐧�(f膩)鍣ㄧ瓑锛屽緸鑰屼娇鍏堕仼鐢ㄤ簬鏁�(sh霉)鎿�(j霉)涓績鍔犻€熷崱銆�5G 鍩虹珯鍜屽叾浠栭€氫俊鍩虹(ch菙)瑷�(sh猫)鏂�銆�

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鍨嬭櫉锛�10AX115U3F45E2SG
銆€銆€鍝佺墝锛欼ntel
銆€銆€绯诲垪锛歋tratix 10
銆€銆€宸ヨ棟绡€(ji茅)榛烇細14nm
銆€銆€閭忚集鍠厓鏁�(sh霉)閲忥細绱� 115K
銆€銆€DSP 妯″鏁�(sh霉)閲忥細~1872
銆€銆€宓屽叆寮忓瓨鍎插櫒锛殈10.8 Mb
銆€銆€鏈€澶х敤鎴� I/O 鏁�(sh霉)閲忥細~594
銆€銆€鏀剁櫦(f膩)鍣ㄩ€熷害锛氭渶楂橀仈 28.3 Gbps
銆€銆€灏佽椤炲瀷锛欶FBGA锛團ine Pitch Flip Chip Ball Grid Array锛�
銆€銆€鏍稿績闆诲锛�0.8V
銆€銆€I/O 闆诲锛�1.0V/1.2V/1.5V/1.8V/2.5V/3.3V

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銆€銆€1. 楂樻€ц兘鏋舵(g貌u)锛氶€氶亷 Intel 鐨� HyperFlex 鎶€琛�(sh霉)鍎�(y艒u)鍖栧悗锛岃兘澶犲湪鐩稿悓鍔熻€椾笅鎻愪緵鏇撮珮鐨勫伐浣滈牷鐜�銆�
銆€銆€2. 寮峰ぇ鐨� DSP 鍔熻兘锛氬寘鍚ぇ閲忓皥鐢ㄧ殑鏁�(sh霉)瀛椾俊铏熻檿鐞嗘ā濉婏紝鑳藉楂樻晥瀹屾垚娴粸閬嬬畻鍜屽京(f霉)闆滄暩(sh霉)瀛�(xu茅)瑷堢畻銆�
銆€銆€3. 楂橀€熶覆琛屾帴鍙ｏ細鏀寔楂橀仈 28.3 Gbps 鐨勬敹鐧�(f膩)鍣ㄩ€熺巼锛屾豢瓒崇従(xi脿n)浠ｉ€氫俊绯荤当(t菕ng)灏嶅付瀵殑闇€姹�銆�
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