5AGXMA7D4F27I5N 鏅傞枔锛�2025/5/10 10:26:38 闁辫畝锛�21

5AGXMA7D4F27I5N 鏄竴娆剧敱鐭ュ悕鍗婂皫(d菐o)楂斿粻鍟嗙敓鐢�(ch菐n)鐨勯珮鎬ц兘 FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛夎姱鐗�锛屽熀浜庡厛閫�(j矛n)鐨勫埗绋嬪伐钘濆埗閫�銆傝┎鑺墖閬╃敤浜庡京(f霉)闆滈倧杓ō(sh猫)瑷�(j矛)鍜岄珮閫熶俊铏熻檿鐞嗗牬鏅紝鍏锋湁楂樺害闈堟椿鎬у拰鍙摯(ku貌)灞曟€�锛屽唬娉涚敤浜庨€氫俊瑷�(sh猫)鍌欍€佹暩(sh霉)鎿�(j霉)涓績鍔犻€�銆佸伐妤�(y猫)鑷嫊鍖栧拰宓屽叆寮忕郴绲�(t菕ng)绛夐牁(l菒ng)鍩�銆�
銆€銆€閫欐 FPGA 鎻愪緵浜嗚睈瀵岀殑 DSP Slice 鍜� Block RAM 璩囨簮锛屾敮鎸佸绋帴鍙ｅ崝(xi茅)璀�锛屽苟鍏峰倷浣庡姛鑰楃壒鎬�銆傚叾鍏�(n猫i)閮ㄦ灦妲�(g貌u)缍�(j墨ng)閬庡劒(y艒u)鍖�锛岃兘澶犳豢瓒抽珮鍚炲悙閲忓拰浣庡欢閬茬殑闇€姹�銆�

鍙冩暩(sh霉)

鍨嬭櫉锛�5AGXMA7D4F27I5N
銆€銆€灏佽椤炲瀷锛欱GA
銆€銆€I/O 鏁�(sh霉)閲忥細1200
銆€銆€閭忚集鍠厓鏁�(sh霉)閲忥細350K
銆€銆€RAM 瀹归噺锛�18MB
銆€銆€DSP Slice 鏁�(sh霉)閲忥細2500
銆€銆€宸ヤ綔闆诲锛�1.0V 鏍稿績 / 1.8V I/O
銆€銆€鏈€澶ф檪閻橀牷鐜囷細1000MHz
銆€銆€鍔熻€楄寖鍦嶏細2W - 15W
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C

鐗规€�

5AGXMA7D4F27I5N 鍏锋湁浠ヤ笅椤憲鐗归粸(di菐n)锛�
銆€銆€1. 楂樻€ц兘锛氶噰鐢ㄦ渶鏂颁竴浠� FPGA 鏋舵(g貌u)锛屾彁渚涘崜瓒婄殑瑷�(j矛)绠楄兘鍔涘拰淇¤櫉铏曠悊鑳藉姏銆�
銆€銆€2. 闈堟椿鎬э細鏀寔閫氶亷纭欢鎻忚堪瑾炶█锛堝 Verilog 鎴� VHDL锛夐€�(j矛n)琛岃嚜瀹氱京瑷�(sh猫)瑷�(j矛)銆�
銆€銆€3. 鎺ュ彛璞愬瘜锛氬吋瀹� PCIe銆丏DR4銆丒thernet 绛夊绋富娴侀€氫俊鍗�(xi茅)璀�銆�
銆€銆€4. 鍔熻€楀劒(y艒u)鍖栵細闆嗘垚鍕曟厠(t脿i)鍔熻€楃鐞嗘妧琛�(sh霉)锛屽彲鏍规摎(j霉)璨�(f霉)杓夎(di脿o)鏁磋兘鑰�銆�
銆€銆€5. 鍙潬鎬э細鍏峰倷鍏�(n猫i)寤鸿嚜妾㈠姛鑳�锛岀⒑淇濋暦鏅傞枔绌�(w臎n)瀹氶亱(y霉n)琛�銆�
銆€銆€6. 灏忓瀷鍖栵細浣跨敤 BGA 灏佽锛岄仼鍚堢穵婀婂瀷瑷�(sh猫)瑷�(j矛)闇€姹傘€�

鎳�(y墨ng)鐢�

瑭茶姱鐗囬仼鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆€銆€1. 閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂斤細濡傚熀绔�銆佽矾鐢卞櫒鍜屼氦鎻涙(j墨)涓殑鏁�(sh霉)鎿�(j霉)鍖呰檿鐞嗘ā濉娿€�
銆€銆€2. 鏁�(sh霉)鎿�(j霉)涓績锛氱敤浣� AI 鍔犻€熷櫒鎴栫恫(w菐ng)绲�(lu貌)鍔熻兘铏涙摤鍖栧钩鑷虹殑鏍稿績绲勪欢銆�
銆€銆€3. 宸ユキ(y猫)鎺у埗锛氬(sh铆)鐝�(xi脿n)寰�(f霉)闆滅殑瀵�(sh铆)鏅傛帶鍒剁郴绲�(t菕ng)鍜屽湒鍍忚檿鐞嗕换鍕�(w霉)銆�
銆€銆€4. 姹借粖闆诲瓙锛氭敮鎸侀珮绱氶椐涜紨鍔╃郴绲�(t菕ng)锛圓DAS锛変腑鎵€闇€鐨勫揩閫熸暩(sh霉)鎿�(j霉)铏曠悊銆�
銆€銆€5. 閱�(y墨)鐧傝ō(sh猫)鍌欙細鐢ㄤ簬瓒呰伈娉㈡垚鍍忓拰鍏朵粬闇€瑕侀珮绮惧害淇¤櫉铏曠悊鐨勬噳(y墨ng)鐢�銆�
銆€銆€6. 娑堣不(f猫i)椤為浕瀛愮敘(ch菐n)鍝侊細鐐洪珮绔濯掗珨鎾斁鍣ㄦ彁渚涜闋荤法瑙ｇ⒓鏀寔銆�