鏅傞枔锛�2023/8/1 11:17:29
闁辫畝锛�466
鐢㈠搧鍨嬭櫉 | 5CEFA9F27C7N |
鎻忚堪 | 闆嗘垚闆昏矾FPGA 336 I/O 672FBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝惧牬鍙法绋嬮杸闄ｅ垪) |
鍒堕�犲晢 | 鑻辩壒鐖� |
绯诲垪 | Cyclone?VE |
鎵撳寘 | 鎵樼洡 |
闆朵欢鐙�鎱�(t脿i) | 娲绘�� |
闆诲-闆绘簮 | 1.07V?1.13V |
宸ヤ綔婧害 | 0掳C?85掳C(TJ) |
鍖呰/绠� | 672-BGA |
渚涙噳鍟嗚ō鍌欏寘瑁� | 672-FBGA(27x27) |
鍩烘湰闆朵欢铏� | 5CEFA9 |
5CEFA9F27C7N
鍙法绋嬮倧杓鍨� | 鐝惧牬鍙法绋嬮杸闄ｅ垪 |
绗﹀悎REACH | 鏄� |
绗﹀悎姝愮洘RoHS | 鏄� |
鐙�鎱�(t脿i) | 娲绘�� |
JESD-30浠ｇ⒓ | S-PBGA-B672 |
杓稿叆鏁搁噺 | 336.0 |
閭忚集鍠厓鏁� | 301000.0 |
杓稿嚭鏁搁噺 | 336.0 |
绔瓙鏁� | 672 |
绺絉AM浣� | 14251008 |
鏈�浣庡伐浣滄韩搴� | 0鈩� |
鏈�楂樺伐浣滄韩搴� | 85鈩� |
闆绘簮 | 1.1,1.2 / 3.3,2.5 |
璩囨牸鐙�鎱�(t脿i) | 涓嶅悎鏍� |
搴ч珮 | 2.0姣背 |
瀛愰鍒� | 鐝惧牬鍙法绋嬮杸闄ｅ垪 |
闆绘簮闆诲妯欑ū | 1.1浼� |
鏈�灏忎緵闆婚浕澹� | 1.07浼� |
鏈�澶ч浕婧愰浕澹� | 1.13浼� |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛� | CMOS |
婧害绛夌礆 | 鍏朵粬 |
绲傜琛ㄦ牸 | 鐞� |
绔瓙闁撹窛 | 1.0姣背 |
绲傜浣嶇疆 | 搴曢儴 |
闀峰害 | 27.0姣背 |
瀵害 | 27.0姣背 |
鍖呰涓婚珨鏉愭枡 | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰浠ｇ⒓ | BGA |
鍖呰绛夋晥浠ｇ⒓ | BGA672,26X26,40 |
鍖呰褰㈢媭 | 寤ｅ牬 |
鍖呰褰㈠紡 | 缍叉牸闄ｅ垪 |
鍒堕�犲晢鍖呰瑾槑 | 绗﹀悎RoHS妯欐簴锛孎BGA-672 |
鐒￠墰鐙�鎱�(t脿i)/RoHS鐙�鎱�(t脿i) | 鐒￠墰/绗﹀悎RoHS |
姘村垎鏁忔劅鎬ф按骞�(MSL) | 3(168灏忔檪) |
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銆俆SMC鐨�28-nm浣庡姛鑰�(28LP)宸ヨ棟鎶�琛�
銆�1.1 V鏍稿績闆诲
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銆傚紩绶氶嵉鍚堜綆楣电礌灏佽
銆傚叿鏈夊吋瀹瑰皝瑁濆昂瀵哥殑澶氱ó瑷倷瀵嗗害锛屽彲鍦ㄤ笉鍚岃ō鍌欏瘑搴︿箣闁撶劇绺伔绉�
銆傜鍚圧oHS鍜屽惈閴�(1)鐨勯伕闋�
?楂樻�ц兘FPGA鏋舵
銆傚叿鏈夊洓鍊嬪瘎瀛樺櫒鐨勫寮峰瀷8杓稿叆ALM
?鍏ч儴瀛樺劜濉�
銆侻10K-甯舵湁杌熺尘閷⒓(ECC)鐨�10鍗�(Kb)鍏у瓨濉�
銆傚瓨鍎插櫒閭忚集闄ｅ垪妯″(MLAB)-640浣嶅垎甯冨紡LUTRAM锛屾偍鍙互鍦ㄥ叾涓娇鐢ㄥ閬�25%鐨凙LM浣滅偤MLAB瀛樺劜鍣�
?宓屽叆寮忕‖IP 妯″
?锛熷嫼鍏欘伋鑿礢P
鈥斿湪鍚屼竴鍙畩绮惧害DSP妯″涓紝鏈鏀寔澶氶仈涓夊�嬩俊铏熻檿鐞嗙簿搴︾礆鍒�(涓夊��9 x 9锛屽叐鍊�18 x 18鎴栦竴鍊�27 x 27涔樻硶鍣�)
鈥�64浣嶇疮鍔犲櫒鍜岀礆鑱�(li谩n)
鈥斿祵鍏ュ紡鍏ч儴绯绘暩瀛樺劜鍣�
鈥旈爯鍔犲櫒/娓涙硶鍣�锛屼互鎻愰珮鏁堢巼
銆傚収瀛樻帶鍒跺櫒
鈥斿叿鏈�16浣嶅拰32浣岴CC鏀寔鐨凞DR3锛孌DR2鍜孡PDDR2
銆傚祵鍏ュ紡鏀剁櫦(f膩)鍣↖ / O
鈥擯CI Express *(PCIe *)Gen2鍜孏en1(x1锛寈2鎴杧4)纭琁P锛屽叿鏈夊鍔熻兘鏀寔锛岀榛炲拰鏍圭鍙�
?鏅傞悩缍茬怠
銆傞珮閬�550 MHz鐨勫叏鐞冩檪閻樼恫绲�
銆傚叏灞�锛岃薄闄愬拰澶栧湇鏅傞悩缍茬怠
銆傚彲浠ラ棞闁夋湭浣跨敤鐨勬檪閻樼恫绲′互闄嶄綆鍕曟厠(t脿i)鍔熻��
?閹栫浉鐠�(hu谩n)(PLL)
銆傜簿纰虹殑鏅傞悩鍚堟垚锛屾檪閻樺欢閬茶鍎熷拰闆跺欢閬茬珐娌�(ZDB)
銆傛暣鏁告ā寮忓拰灏忔暩妯″紡
?FPGA閫氱敤I / O(GPIO)
銆�875 Mbps鐨凩VDS鎺ユ敹鍣ㄥ拰840 Mbps鐨凩VDS 鐧�(f膩)閫佸櫒
銆�400 MHz / 800 Mbps澶栭儴瀛樺劜鍣ㄦ帴鍙�
路鐗囦笂鍖归厤(OCT)
路 3.3 V鏀寔锛屾渶楂�16 mA椹呭嫊寮峰害
?浣庡姛鑰楅珮閫熶覆琛屾帴鍙�
銆�614 Mbps鑷�6.144 Gbps闆嗘垚鏀剁櫦(f膩)鍣ㄩ�熷害
銆傚偝杓搁爯鍔犻噸鍜屾帴鏀舵鍧囪
銆傚�嬪垾閫氶亾鐨勫嫊鎱�(t脿i)閮ㄥ垎閲嶆柊閰嶇疆
?HPS (鍍匔yclone V SE锛孲X 鍜孲T瑷倷)
銆傚柈鏍告垨闆欐牳Arm Cortex-A9 MPCore铏曠悊鍣�-鏈�楂橀牷鐜囧彲閬�925 MHz锛屽苟鏀寔灏嶇ū鍜岄潪灏嶇ū澶氳檿鐞�
銆傛帴鍙ｅ鍦嶈ō鍌�-10/100/1000浠ュお缍插獟楂旇í鍟忔帶鍒�(EMAC)锛孶SB 2.0 On-The-GO(OTG)鎺у埗鍣�锛屽洓涓插彛澶栧湇鎺ュ彛(QSPI)闁冨瓨鎺у埗鍣紝NAND 闁冨瓨鎺у埗鍣�锛屽畨鍏ㄦ暩瀛�/澶氬獟楂斿崱(SD / MMC)鎺у埗鍣�锛孶ART锛屾帶鍒跺櫒灞�鍩熺恫(CAN)锛屼覆琛屽鍦嶈ō鍌欐帴鍙�(SPI)锛孖2C鎺ュ彛浠ュ強澶氶仈85鍊婬PS GPIO 鎺ュ彛
銆傜郴绲�(t菕ng)澶栬ō-閫氱敤瀹氭檪鍣�锛岀湅闁�鐙楀畾鏅傚櫒锛岀洿鎺ュ瓨鍎插櫒瑷晱(DMA)鎺у埗鍣�锛孎PGA閰嶇疆绠＄悊鍣ㄤ互鍙婃檪閻樺拰寰╀綅绠＄悊鍣�
銆傜墖涓奟AM鍜屽紩灏嶳OM
銆侶PS-FPGA姗嬫帴鍣�-鍖呮嫭FPGA鍒癏PS锛孒PS鍒癋PGA鍜岃紩鍨婬PS鍒癋PGA鐨勬⿱鎺ュ櫒锛岄�欎簺姗嬫帴鍣ㄥ厑瑷盕PGA鏋舵鍚慔PS涓殑寰炲爆鐧�(f膩)鍑轰簨鍕欙紝鍙嶄箣浜︾劧
銆侳PGA鍒癏PS SDRAM鎺у埗鍣ㄥ瓙绯荤当(t菕ng)-鎻愪緵鑸嘓PS SDRAM鎺у埗鍣ㄧ殑澶氱鍙ｅ墠绔�(MPFE)鐨勫彲閰嶇疆鎺ュ彛
銆侫rm CoreSight?JTAG瑾胯│瑷晱绔彛锛岃窡韫ょ鍙ｅ拰鐗囦笂璺熻工瀛樺劜
?閰嶇疆
銆傜鏀逛繚璀�-鍏ㄩ潰鐨勮ō瑷堜繚璀�锛屽彲淇濊鎮ㄥ璨寸殑IP鎶曡硣
銆傚寮风殑楂樼礆鍔犲瘑妯欐簴(AES)瑷▓瀹夊叏鍔熻兘
銆侰vP
銆侳PGA鐨勫嫊鎱�(t脿i)閲嶉厤缃�
銆傛湁婧愪覆琛�(AS)x1鍜寈4锛岀劇婧愪覆琛�(PS)锛孞TAG鍜屽揩閫熺劇婧愬苟琛�(FPP)x8鍜寈16閰嶇疆閬搁爡
銆傚収閮ㄦ摝娲�
銆傞儴鍒嗛噸鏂伴厤缃�
5CEFA9F27C7N绗﹁櫉
5CEFA9F27C7N鑵冲嵃
