鏅傞枔锛�2023/8/1 11:11:08
闁辫畝锛�320
鐢�(ch菐n)鍝佸瀷铏� | EP1S20F780I6N |
鎻忚堪 | 闆嗘垚闆昏矾FPGA 586 I/O 780FBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鍒堕�犲晢 | 鑻辩壒鐖� |
绯诲垪 | Stratix? |
鎵撳寘 | 鎵樼洡 |
闆朵欢鐙�鎱�(t脿i) | 閬庢檪鐨� |
闆诲-闆绘簮 | 1.425V?1.575V |
宸ヤ綔婧害 | -40掳C?100掳C(TJ) |
鍖呰/绠� | 780-BBGA锛孎(xi脿n)CBGA |
渚涙噳鍟嗚ō鍌欏寘瑁� | 780-FBGA(29x29) |
鍩烘湰闆朵欢铏� | EP1S20 |
EP1S20F780I6N
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
绗﹀悎REACH | 鏄� |
绗﹀悎姝愮洘RoHS | 鏄� |
鐙�鎱�(t脿i) | 杞�(zhu菐n)鍏� |
JESD-30浠ｇ⒓ | S-PBGA-B780 |
JESD-609浠ｇ⒓ | 1铏� |
绺絉AM浣� | 1669248 |
CLB鏁�(sh霉)閲� | 2132.0 |
杓稿叆鏁�(sh霉)閲� | 586.0 |
閭忚集鍠厓鏁�(sh霉) | 18460.0 |
杓稿嚭鏁�(sh霉)閲� | 586.0 |
绔瓙鏁�(sh霉) | 780 |
绲勭箶 | 2132 CLBS |
宄板�煎洖娴佹韩搴�(鈩�) | 245 |
闆绘簮 | 1.5,1.5 / 3.3 |
璩囨牸鐙�鎱�(t脿i) | 涓嶅悎鏍� |
搴ч珮 | 3.5姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲妯欑ū | 1.5浼� |
鏈�灏忎緵闆婚浕澹� | 1.425浼� |
鏈�澶ч浕婧愰浕澹� | 1.575浼� |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛�(sh霉) | CMOS |
绲傜瀹屾垚 | 閷妧閵� |
绲傜琛ㄦ牸 | 鐞� |
绔瓙闁撹窛 | 1.0姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅傞枔@宄板�煎洖娴佹韩搴︽渶澶у��(绉�) | 40 |
闀峰害 | 29.0姣背 |
瀵害 | 29.0姣背 |
鍖呰涓婚珨鏉愭枡 | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰浠ｇ⒓ | BGA |
鍖呰绛夋晥浠ｇ⒓ | BGA780,28X28,40 |
鍖呰褰㈢媭 | 寤ｅ牬 |
鍖呰褰㈠紡 | 缍�(w菐ng)鏍奸櫍鍒� |
鍒堕�犲晢鍖呰瑾槑 | 29 X 29 MM锛�1 MM闁撹窛锛岀劇閴�锛孎(xi脿n)BGA-780 |
鐒￠墰鐙�鎱�(t脿i) | 鐒￠墰 |
姘村垎鏁忔劅鎬ф按骞�(MSL) | 3(168灏忔檪) |
10,570鑷�79,040 LE 瑕嬭〃1-1
澶氶仈7,427,520鍊婻AM浣�(928,440瀛楃瘈(ji茅))鍙敤锛岃�屼笉娓涘皯閭忚集璩囨簮
TriMatrixTM瀛樺劜鍣�锛岀敱涓夌óRAM濉婂ぇ灏忕祫鎴愶紝浠ュ鐝�(xi脿n)鐪熸鐨勯洐绔彛瀛樺劜鍣ㄥ拰鍏堥�插厛鍑�(FIFO)绶╂矕鍗�(q奴)
楂橀�烡SP妯″鎻愪緵涔樻硶鍣�(蹇簬300 MHz)锛屼箻娉曠疮鍔犲姛鑳藉拰鏈夐檺鑴堟矕闊挎噳(FIR)婵炬尝鍣ㄧ殑灏堢敤瀵︾従(xi脿n)
澶氶仈16鍊嬪叏灞�鏅傞悩锛屾瘡鍊嬭ō鍌欏崁(q奴)鍩熷叿鏈�22鍊嬫檪閻樿硣婧�
姣忓�嬭ō鍌欏閬�12鍊婸LL(鍥涘�嬪寮峰瀷PLL鍜屽叓鍊嬪揩閫烶LL)鍙彁渚涙摯闋伙紝鍙法绋嬪付瀵�锛屾檪閻樺垏鎻涳紝瀵︽檪PLL閲嶉厤缃互鍙婇珮绱氫箻娉曞拰鐩哥Щ
鏀寔澶氱ó鍠鍜屽樊鍒咺 / O妯欐簴
鍦ㄥ閬�116鍊嬮�氶亾涓婃敮鎸侀珮閫熷樊鍒咺 / O锛屽叾涓閬�80鍊嬮�氶亾閲濆皪840鍏嗘瘮鐗�(Mbps)閫茶浜嗗劒(y艒u)鍖�
鏀寔楂橀�熺恫(w菐ng)绲″拰閫氫俊绺界窔妯欐簴锛屽寘鎷琑apidIO锛孶TOPIA IV锛孋SIX锛孒yperTransportTM鎶�琛�(sh霉)锛�10G浠ュお缍�(w菐ng)XSBI锛孲PI-4闅庢2(POS-PHY绱氬垾4)锛屽拰SFI-4
灏峀VDS鐨勫樊鍒嗙墖涓婂尮閰嶆敮鎸�
鏀寔楂橀�熷閮ㄥ瓨鍎插櫒锛屽寘鎷浂绺界窔鍛ㄨ綁(zhu菐n)(ZBT)SRAM锛屽洓鏁�(sh霉)鎿�(j霉)閫熺巼(QDR鍜孮DRII)SRAM锛岄洐鏁�(sh霉)鎿�(j霉)閫熺巼(DDR)SDRAM锛孌DR蹇�熷懆鏈烺AM(FCRAM)鍜屽柈鏁�(sh霉)鎿�(j霉)閫熺巼(SDR) )SDRAM
鍦�-6鍜屾洿楂橀�熷害绱氬垾鐨勮ō鍌欎腑鏀寔66-MHz PCI(64鍜�32浣�)锛屽湪-8鍜屾洿蹇�熷害绱氬垾鐨勮ō鍌欎腑鏀寔33-MHz PCI(64鍜�32浣�)
鍦�-5閫熷害绛夌礆鐨勮ō鍌欎腑鏀寔133 MHz PCI-X 1.0
鍦�-6鍜屾洿楂橀�熷害绛夌礆鐨勮ō鍌欎腑鏀寔100 MHz PCI-X 1.0
鍦�-7閫熺礆瑷倷涓敮鎸�66-MHz PCI-X 1.0
鏀寔AlteraMegaCore?鍔熻兘鍜孉ltera Megafunction Partners Program(AMPPSM)瀹忓姛鑳戒腑鐨勫鍊嬬煡璀樼敘(ch菐n)娆�(qu谩n)瀹忓姛鑳�
鏀寔閬犵▼閰嶇疆鏇存柊
EP1S20F780I6N绗﹁櫉
EP1S20F780I6N鑵冲嵃
