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闁辫畝锛�12
EP2AGX65CU17C6N 鏄敱 Altera锛堢従(xi脿n)鐐� Intel FPGA锛夊叕鍙哥敓鐢�(ch菐n)鐨勪竴娆鹃珮鎬ц兘 FPGA 鑺墖锛屽爆浜� Arria GX 绯诲垪銆傝┎绯诲垪 FPGA 闆嗘垚浜嗚睈瀵岀殑閭忚集璩囨簮鍜屾敹鐧�(f膩)鍣ㄥ姛鑳�锛岄仼鐢ㄤ簬閫氫俊銆佸伐妤�(y猫)鎺у埗銆佸唬鎾闋讳互鍙婂叾浠栭渶瑕侀珮甯跺鏁�(sh霉)鎿�(j霉)铏曠悊鐨勬噳鐢ㄥ牬鏅�銆�
銆�銆�Arria GX 绯诲垪浠ュ叾浣庢垚鏈拰楂樿兘鏁堣憲绋�锛屽悓鏅傛彁渚涗簡寮峰ぇ鐨勪俊铏熻檿鐞嗚兘鍔涘拰闈堟椿鐨� I/O 鏀寔锛岃兘澶犳豢瓒冲绋京闆滅郴绲�(t菕ng)瑷�(sh猫)瑷堢殑闇�姹�銆�
鍨嬭櫉锛欵P2AGX65CU17C6N
銆�銆�鍝佺墝锛欰ltera锛圛ntel FPGA锛�
銆�銆�绯诲垪锛欰rria GX
銆�銆�FPGA 鏋舵(g貌u)锛歋tratix II 鎶�琛�(sh霉)琛嶇敓
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 65,000 鍊�
銆�銆�RAM 璩囨簮锛氱磩 4.8 Mb
銆�銆�DSP 妯″锛氭敮鎸佸閬� 120 鍊� 18x18 涔樻硶鍣�
銆�銆�鏀剁櫦(f膩)鍣ㄩ�氶亾锛氭渶澶氭敮鎸� 8 鍊嬩覆琛屾敹鐧�(f膩)鍣�
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼鑼冨湇锛�312 Mbps 鑷� 3.75 Gbps
銆�銆�I/O 鏁�(sh霉)閲忥細瓒呴亷 440 鍊�
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�灏佽褰㈠紡锛欶BGA 1020
EP2AGX65CU17C6N 鍏峰倷浠ヤ笅涓昏鐗规�э細
銆�銆�1. 楂樻�ц兘 FPGA 鏋舵(g貌u)锛氬熀浜� Stratix II 鎶�琛�(sh霉)骞宠嚭闁嬬櫦(f膩)锛屾彁渚涘嚭鑹茬殑鏅傚簭鎬ц兘鍜岃硣婧愬埄鐢ㄧ巼銆�
銆�銆�2. 寮峰ぇ鐨勬敹鐧�(f膩)鍣ㄥ姛鑳斤細闆嗘垚澶氬�嬮珮閫熶覆琛屾敹鐧�(f膩)鍣�锛屽彲鏀寔鍖呮嫭 PCIe銆乆AUI 鍜� CPRI 鍦ㄥ収(n猫i)鐨勫绋崝(xi茅)璀般��
銆�銆�3. 闈堟椿鐨勯倧杓垏瀛樺劜璩囨簮锛氭搧鏈夎睈瀵岀殑閭忚集鍠厓銆佸祵鍏ュ紡 RAM 濉婁互鍙� DSP 妯″锛岄仼鍚堝京闆滅殑绠楁硶瀵︾従(xi脿n)銆�
銆�銆�4. 浣庡姛鑰楄ō(sh猫)瑷堬細閲囩敤鍏堥�茬殑鍒堕�犲伐钘濆拰鍎�(y艒u)鍖栨灦妲�(g貌u)锛屽湪淇濇寔楂樻�ц兘鐨勫悓鏅傞檷浣庡姛鑰�銆�
銆�銆�5. 寤ｆ硾鐨� I/O 妯欐簴鏀寔锛氬吋瀹瑰绋妤�(y猫)妯欐簴鎺ュ彛锛屽 LVDS銆丩VCMOS 绛�锛屾柟渚胯垏澶栭儴瑷�(sh猫)鍌欓�ｆ帴銆�
銆�銆�6. 鍙潬鎬ч珮锛氭敮鎸侀儴鍒嗛噸鏂伴厤缃拰鍦ㄧ窔鏇存柊鍔熻兘锛岄仼鎳夊嫊鎱�(t脿i)鐠�(hu谩n)澧冮渶姹�銆�
EP2AGX65CU17C6N 涓昏鎳夌敤浜庝互涓嬮牁(l菒ng)鍩燂細
銆�銆�1. 閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂斤細渚嬪鐒＄窔鍩虹珯銆佸厜绾栨帴鍏ヨō(sh猫)鍌欎腑鐨勬暩(sh霉)鎿�(j霉)鍌宠几鑸囪檿鐞�銆�
銆�銆�2. 宸ユキ(y猫)鑷嫊鍖栵細鐢ㄤ簬瀵︽檪鎺у埗鍜屽湒鍍忚檿鐞嗕换鍕�銆�
銆�銆�3. 瑕栭牷鑸囧唬鎾細鏀寔楂樻竻鎴栬秴楂樻竻瑕栭牷娴佺殑绶ㄧ⒓瑙ｇ⒓鍙婃牸寮忚綁(zhu菐n)鎻�銆�
銆�銆�4. 娓│娓噺锛氱敤浣滃京闆滀俊铏熺敓鎴愭垨鍒嗘瀽鐨勬牳蹇冪祫浠�銆�
銆�銆�5. 閱�(y墨)鐧傛垚鍍忥細瀵︾従(xi脿n)蹇�熸暩(sh霉)鎿�(j霉)閲囬泦鑸囬噸寤洪亱绠椼��
銆�銆�6. 宓屽叆寮忚▓绠楋細浣滅偤灏忓瀷鍖栭珮鎬ц兘瑷堢畻骞宠嚭鐨勪竴閮ㄥ垎銆�
EP2AGX65F780I7, EP2AGX65G780C8
