鏅傞枔锛�2023/8/1 11:05:40
闁辫畝锛�469
鐢�(ch菐n)鍝佸瀷铏� | EP2C35F484I8 |
鎻忚堪 | IC FPGA 322 I/O 484FBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鍒堕�犲晢 | 鑻辩壒鐖� |
绯诲垪 | Cyclone?II |
鎵撳寘 | 鎵樼洡 |
闆朵欢鐙�鎱�(t脿i) | 娲绘�� |
闆诲-闆绘簮 | 1.15V?1.25V |
宸ヤ綔婧害 | -40掳C?100掳C(TJ) |
鍖呰/绠� | 484-BGA |
渚涙噳鍟嗚ō鍌欏寘瑁� | 484-FBGA(23x23) |
鍩烘湰闆朵欢铏� | EP2C35 |
EP2C35F484I8
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
鐙�鎱�(t脿i) | 杞�(zhu菐n)鍏� |
鏈�澶ф檪閻橀牷鐜� | 402.5鍏嗚但 |
JESD-30浠ｇ⒓ | S-PBGA-B484 |
JESD-609浠ｇ⒓ | 00 |
绺絉AM浣� | 483840 |
CLB鏁�(sh霉)閲� | 2076.0 |
杓稿叆鏁�(sh霉)閲� | 322.0 |
閭忚集鍠厓鏁�(sh霉) | 33216.0 |
杓稿嚭鏁�(sh霉)閲� | 306.0 |
绔瓙鏁�(sh霉) | 484 |
绲勭箶 | 2076 CLBS |
宄板�煎洖娴佹韩搴�(鈩�) | 220 |
闆绘簮 | 1.2,1.5 / 3.3,3.3 |
璩囨牸鐙�鎱�(t脿i) | 涓嶅悎鏍� |
搴ч珮 | 2.6姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲妯欑ū | 1.2浼� |
鏈�灏忎緵闆婚浕澹� | 1.15浼� |
鏈�澶ч浕婧愰浕澹� | 1.25浼� |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛�(sh霉) | CMOS |
绲傜瀹屾垚 | 閷�/閴�(Sn63Pb37) |
绲傜琛ㄦ牸 | 鐞� |
绔瓙闁撹窛 | 1.0姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅傞枔@宄板�煎洖娴佹韩搴︽渶澶у��(绉�) | 20 |
闀峰害 | 23.0姣背 |
瀵害 | 23.0姣背 |
闄勫姞鍔熻兘 | 閭勯渶瑕�3.3渚涙噳 |
鍖呰涓婚珨鏉愭枡 | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰浠ｇ⒓ | BGA |
鍖呰绛夋晥浠ｇ⒓ | BGA484,22X22,40 |
鍖呰褰㈢媭 | 寤ｅ牬 |
鍖呰褰㈠紡 | 缍�(w菐ng)鏍奸櫍鍒� |
鍒堕�犲晢鍖呰瑾槑 | FBGA-484 |
鐒￠墰鐙�鎱�(t脿i)/RoHS鐙�鎱�(t脿i) | 鍖呭惈閴�/ RoHS涓嶅悎瑕�(gu墨) |
姘村垎鏁忔劅鎬ф按骞�(MSL) | 3(168灏忔檪) |
鈻犲叿鏈�4,608鑷�68,416 LE鐨勯珮瀵嗗害鏋舵(g貌u)
M4K宓屽叆寮忓瓨鍎插
楂橀仈1.1 Mbit鐨勫彲鐢≧AM锛岃�屼笉鏈冩笡灏戝彲鐢ㄩ倧杓�
姣忓�嬪4,096鍊嬪瓨鍎蹭綅(姣忓�嬪4,608鍊嬩綅锛屽寘鎷�512鍊嬪鍋舵牎椹椾綅)
脳1锛屆�2锛屆�4锛屆�8锛屆�9锛屆�16锛屆�18锛屆�32鍜屆�36鐨勫彲璁婄鍙ｉ厤缃�
閬╃敤浜幟�1锛屆�2锛屆�4锛屆�8锛屆�9锛屆�16鍜屆�18妯″紡鐨勭湡姝ｉ洐绔彛(涓�娆¤畝鍙栧拰涓�娆″鍏�锛屽叐娆¤畝鍙栨垨鍏╂瀵叆)鎿嶄綔
瀛楃瘈(ji茅)鍙湪瀵叆鏈熼枔灞忚斀鏁�(sh霉)鎿�(j霉)杓稿叆
鏈�楂�260MHz鐨勫伐浣滈牷鐜�
鈻犲祵鍏ュ紡涔樻硶鍣�
鏈�澶氬彲灏�150鍊�18脳18浣嶄箻娉曞櫒閰嶇疆鐐哄叐鍊嬬崹绔嬬殑9脳9浣嶄箻娉曞櫒锛屾�ц兘楂橀仈250 MHz
鍙伕鐨勮几鍏ュ拰杓稿嚭瀵勫瓨鍣�
鈻犻珮绱欼 / O鏀寔
楂橀�熷樊鍒咺 / O妯欐簴鏀寔锛屽寘鎷琇VDS锛孯SDS锛宮ini-LVDS锛孡VPECL锛屽樊鍒咹STL鍜屽樊鍒哠STL
鍠I / O妯欐簴鏀寔锛屽寘鎷�2.5 V鍜�1.8 V锛孲STL I鍜孖I椤烇紝1.8 V鍜�1.5 V HSTL I鍜孖I椤�锛�3.3 V PCI鍜孭CI-X 1.0銆�3.3- 锛�2.5V锛�1.8V鍜�1.5V LVCMOS浠ュ強3.3V锛�2.5V鍜�1.8V LVTTL
澶栧湇绲勪欢浜掗�ｇ壒娈婂埄鐩婄祫(PCI SIG)PCI鏈湴绺界窔瑕�(gu墨)鑼冿紝淇▊鐗�3.0绗﹀悎鍦�32鎴�64浣嶆帴鍙ｄ笂浠�33鎴�66 MHz閬嬭3.3 V鐨勮姹�
鍏锋湁澶栭儴TI PHY鍜孉ltera PCI Express脳1Megacore?鍔熻兘鐨凱CI Express
133 MHz PCI-X 1.0瑕�(gu墨)鏍煎吋瀹规��
楂橀�熷閮ㄥ瓨鍎插櫒鏀寔锛屽寘鎷珼DR锛孌DR2 鍜孲DR SDRAM锛屼互鍙奞DRII SRAM锛孉ltera IP MegaCore鍔熻兘鐨勫姞鍏ョ偤瀹冨�戞彁渚涗簡鏄撶敤鎬�
姣忓�婭 / O鍏冪礌(IOE)涓夊�嬪皥鐢ㄥ瘎瀛樺櫒锛氫竴鍊嬭几鍏ュ瘎瀛樺櫒锛屼竴鍊嬭几鍑哄瘎瀛樺櫒鍜屼竴鍊嬭几鍑轰娇鑳藉瘎瀛樺櫒
鍙法绋嬬附绶氫繚鎸佸姛鑳�
鍙法绋嬭几鍑洪﹨(q奴)鍕曞挤搴﹀姛鑳�
寰炲紩鑵冲埌IOE鎴栭倧杓櫍鍒楃殑鍙法绋嬪欢閬�
I / O绲勫垎绲�锛岀敤浜庡敮涓�鐨刅CCIO鍜�/鎴朧REF绲勮ō缃�
MultiVolt?I / O妯欐簴鏀寔1.5銆�1.8銆�2.5鍜�3.3鎺ュ彛
鐔辨彃鎷旀搷浣滄敮鎸�
鍦ㄩ厤缃箣鍓嶅拰閰嶇疆鏈熼枔锛孖 / O寮曡叧涓婃媺鐙�鎱�(t脿i)杓冨急鐨勪笁鎱�(t脿i)
鍙法绋嬫紡妤甸枊璺几鍑�
绯诲垪鐗囦笂鍖归厤鏀寔
鈻犻潏娲荤殑鏅傞悩绠＄悊闆昏矾
鍒嗗堡鏅傞悩缍�(w菐ng)绲�锛屾�ц兘楂橀仈402.5 MHz
姣忓�嬭ō鍌欐渶澶氬洓鍊婸LL鎻愪緵鏅傞悩涔樻硶鍜岄櫎娉�锛岀浉绉伙紝鍙法绋嬪崰绌烘瘮鍜屽閮ㄦ檪閻樿几鍑�锛屽緸鑰屽厑瑷辩郴绲�(t菕ng)绱氭檪閻樼鐞嗗拰鍋忔枩鎺у埗
鍏ㄥ眬鏅傞悩缍�(w菐ng)绲′腑澶氶仈16姊濆叏灞�鏅傞悩绶�锛岄﹨(q奴)鍕曟暣鍊嬭ō鍌�
鈻犺ō鍌欓厤缃�
蹇�熺殑涓茶閰嶇疆鍏佽ū閰嶇疆鏅傞枔灏戜簬100姣
瑙ｅ绺姛鑳藉彲娓涘皯绋嬪簭鏂囦欢鐨勫瓨鍎插苟绺煭閰嶇疆鏅傞枔
鏀寔澶氱ó閰嶇疆妯″紡锛氫富鍕曚覆琛�锛岃鍕曚覆琛屽拰鍩轰簬JTAG鐨勯厤缃�
鏀寔閫氶亷浣庢垚鏈覆琛岄厤缃ō鍌欓�茶閰嶇疆
瑷倷閰嶇疆鏀寔澶氱ó闆诲(3.3銆�2.5 鎴�1.8 V)
鈻犵煡璀樼敘(ch菐n)娆�(qu谩n)
Altera瀹忓姛鑳藉拰Altera MegaCore鍔熻兘鏀寔浠ュ強Altera瀹忓姛鑳藉悎浣滀紮浼磋▓鍔�(AMPPSM)瀹忓姛鑳芥敮鎸�锛岄仼鐢ㄤ簬寤ｆ硾鐨勫祵鍏ュ紡铏曠悊鍣紝鐗囦笂鍜岀墖澶栨帴鍙�锛屽鍦嶅姛鑳�锛孌SP鍔熻兘浠ュ強閫氫俊鍔熻兘鍜屽崝(xi茅)璀般�傝í鍟弚ww.altera.com涓婄殑Altera IPMegaStore锛屼笅杓塈P MegaCore鍔熻兘銆�
Nios II宓屽叆寮忚檿鐞嗗櫒鏀寔Cyclone II绯诲垪鐐哄櫒浠舵彁渚涗簡蹇�熶笂闆诲姛鑳�锛岃┎鍔熻兘鍙姞蹇笂闆诲京浣�(POR)鏅傞枔銆傛敮鎸佸揩閫熷暉鍕曞姛鑳界殑瑷倷鍦ㄨō鍌欒▊璩间唬纰间腑妯欐湁鈥� A鈥�銆備緥濡傦紝EP2C5A锛孍P2C8A锛孍P2C15A鍜孍P2C20A銆侲P2C5A 鍍呴仼鐢ㄤ簬姹借粖閫熷害绛夌礆銆侲P2C8A鍜孍P2C20A 鍍呴仼鐢ㄤ簬宸ユキ(y猫)閫熷害绛夌礆銆侲P2C15A鍍呭叿鏈夊揩閫熸帴閫氬姛鑳�锛屽苟涓斿彲鐢ㄤ簬鍟嗘キ(y猫)绱氬拰宸ユキ(y猫)绱氥�傞櫎浜嗘敮鎸佹洿蹇殑POR鏅傞枔浠ュ锛孋yclone II鈥� A鈥濆櫒浠跺湪鍔熻兘鍜屽姛鑳戒笂鑸囬潪A鍣ㄤ欢鐩稿悓銆�
EP2C35F484I8绗﹁櫉
EP2C35F484I8鑵冲嵃
