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銆€銆€Stratix II 绯诲垪閲囩敤浜嗗厛閫�(j矛n)鐨� 90nm 宸ヨ棟鎶€琛�(sh霉)锛屾敮鎸侀珮閫熸敹鐧�(f膩)鍣�锛屽叿鍌欏挤(qi谩ng)澶х殑骞惰铏曠悊鑳藉姏鍜屼綆鍔熻€楃壒鎬�锛岄仼鍚堣姹傚毚(y谩n)鏍肩殑宸ユキ(y猫)鍜岄€氫俊鐠�(hu谩n)澧�銆�

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鍨嬭櫉(h脿o)锛欵P2S90F1020I5N
銆€銆€绯诲垪锛歋tratix II
銆€銆€鍒堕€犲晢锛欰ltera锛圛ntel FPGA锛�
銆€銆€FPGA 閭忚集鍠厓鏁�(sh霉)锛氱磩 89,376
銆€銆€閰嶇疆闁冨瓨瀹归噺锛氱劇鍏�(n猫i)缃厤缃杻瀛�
銆€銆€I/O 寮曡叧鏁�(sh霉)锛�1020
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆€銆€灏佽椤炲瀷锛欶BGA
銆€銆€宸ヨ棟绡€(ji茅)榛�(di菐n)锛�90nm
銆€銆€渚涢浕闆诲锛氭牳蹇冮浕澹� 1.2V锛孖/O 闆诲 1.5V/1.8V/2.5V/3.3V
銆€銆€瀛樺劜(ch菙)鍣ㄨ硣婧愶細澶氶仈(d谩) 4.7Mb 鐨勫祵鍏ュ紡 RAM
銆€銆€DSP 妯″锛氬閬�(d谩) 288 鍊�(g猫) 18x18 涔樻硶鍣�
銆€銆€鏅�(sh铆)閻樼鐞嗭細PLL 鍜� DCM
銆€銆€鏀剁櫦(f膩)鍣ㄩ€熺巼锛氭渶楂樺彲閬�(d谩) 6.375 Gbps

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