EP3SL150F780I3G 鏅傞枔锛�2025/5/20 14:03:46 闁辫畝锛�20

EP3SL150F780I3G 鏄� Altera 鍏徃锛堢従(xi脿n)鐐� Intel FPGA 闆嗗湗(tu谩n)锛夋帹鍑虹殑 Stratix III 绯诲垪 FPGA 鑺墖涓殑涓€鍝�銆係tratix III 绯诲垪 FPGA 鎻愪緵楂樻€ц兘鍜岄珮瀵嗗害鐨勯倧杓硣婧愶紝閬╁悎寰�(f霉)闆滀俊铏熻檿鐞�銆侀€氫俊绯荤当(t菕ng)銆佸湒鍍忚檿鐞嗕互鍙婂祵鍏ュ紡瑷�(j矛)绠楃瓑鎳�(y墨ng)鐢ㄩ牁(l菒ng)鍩�銆�
銆€銆€EP3SL150F780I3G 鍩轰簬 65nm 宸ヨ棟鍒堕€�锛屽叿鏈夎睈瀵岀殑 DSP 妯″銆佸祵鍏ュ紡瀛樺劜鍣ㄥ鍜岄珮閫熸敹鐧�(f膩)鍣�锛岃兘澶犳豢瓒冲绋珮鎬ц兘瑷�(j矛)绠楅渶姹�銆�

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鍨嬭櫉锛欵P3SL150F780I3G
銆€銆€宸ヨ棟鍒剁▼锛�65nm
銆€銆€I/O 鏁�(sh霉)閲忥細540
銆€銆€閭忚集鍠厓鏁�(sh霉)閲忥細149,280
銆€銆€宓屽叆寮忓瓨鍎插櫒瀹归噺锛�6.1 Mb
銆€銆€DSP 妯″鏁�(sh霉)閲忥細240
銆€銆€閰嶇疆妯″紡锛氫富鍕曚覆琛� (AS) 鍜岃鍕曚覆琛� (PS)
銆€銆€灏佽椤炲瀷锛欶BGA
銆€銆€灏佽灏哄锛�780 寮曡叧
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C

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EP3SL150F780I3G 鍏峰倷浠ヤ笅闂�(gu膩n)閸电壒鎬э細
銆€銆€1. 楂樻€ц兘閭忚集绲�(ji茅)妲�(g貌u)锛氶噰鐢� Stratix III 绯诲垪鐗规湁鐨勬灦妲�(g貌u)瑷�(sh猫)瑷�(j矛)锛屾敮鎸侀珮閬�(d谩) 450 MHz 鐨勫収(n猫i)閮ㄦ檪閻橀牷鐜囥€�
銆€銆€2. 瀵屽惈 DSP 鍔熻兘锛氬寘鍚閬�(d谩) 240 鍊嬪皥鐢� DSP 妯″锛屾瘡鍊嬫ā濉婂彲浠ュ(sh铆)鐝�(xi脿n)寰�(f霉)闆滄暩(sh霉)瀛�(xu茅)閬�(y霉n)绠楀拰婵炬尝鍔熻兘銆�
銆€銆€3. 澶у閲忓瓨鍎插櫒锛氶泦鎴� 6.1Mb 鐨勫祵鍏ュ紡瀛樺劜鍣ㄥ锛岀敤浜庢暩(sh霉)鎿�(j霉)绶╁瓨鍜岃嚚鏅傚瓨鍎层€�
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