鏅傞枔锛�2023/8/1 11:20:40
闁辫畝锛�1007
鐢㈠搧鍨嬭櫉 | EP4SGX110HF35C3N |
鎻忚堪 | 闆嗘垚闆昏矾FPGA 488 I/O 1152FBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鍒堕�犲晢 | 鑻辩壒鐖� |
绯诲垪 | Stratix?IV GX |
鎵撳寘 | 鎵樼洡 |
闆朵欢鐙�鎱�(t脿i) | 閬庢檪鐨� |
闆诲-闆绘簮 | 0.87V?0.93V |
宸ヤ綔婧害 | 0掳C?85掳C(TJ) |
鍖呰/绠� | 1152-BBGA锛孎(xi脿n)CBGA |
渚涙噳鍟嗚ō鍌欏寘瑁� | 1152-FBGA(35x35) |
鍩烘湰闆朵欢铏� | EP4SGX110 |
EP4SGX110HF35C3N
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
绗﹀悎姝愮洘RoHS | 鏄� |
鐙�鎱�(t脿i) | 杞夌Щ |
鏈�澶ф檪閻橀牷鐜� | 717.0鍏嗚但 |
JESD-30浠ｇ⒓ | S-PBGA-B1152 |
JESD-609浠ｇ⒓ | 1铏� |
绺絉AM浣� | 9793536 |
CLB鏁搁噺 | 42240.0 |
杓稿叆鏁搁噺 | 488.0 |
閭忚集鍠厓鏁� | 105600.0 |
杓稿嚭鏁搁噺 | 488.0 |
绔瓙鏁� | 1152 |
鏈�浣庡伐浣滄韩搴� | 0鈩� |
鏈�楂樺伐浣滄韩搴� | 85鈩� |
绲勭箶 | 42240 CLBS |
宄板�煎洖娴佹韩搴�(鈩�) | 245 |
闆绘簮 | 0.9,1.2 / 3,1.5,2.5 |
璩囨牸鐙�鎱�(t脿i) | 涓嶅悎鏍� |
搴ч珮 | 3.6姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲妯欑ū | 0.9浼� |
鏈�灏忎緵闆婚浕澹� | 0.87浼� |
鏈�澶ч浕婧愰浕澹� | 0.93浼� |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛� | CMOS |
婧害绛夌礆 | 鍏朵粬 |
绲傜瀹屾垚 | 閷�/閵�/閵�(Sn / Ag / Cu) |
绲傜琛ㄦ牸 | 鐞� |
绔瓙闁撹窛 | 1.0姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅傞枔@宄板�煎洖娴佹韩搴︽渶澶у��(绉�) | 40 |
闀峰害 | 35.0姣背 |
瀵害 | 35.0姣背 |
鍖呰涓婚珨鏉愭枡 | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰浠ｇ⒓ | BGA |
鍖呰绛夋晥浠ｇ⒓ | BGA1152,34X34,40 |
鍖呰褰㈢媭 | 寤ｅ牬 |
鍖呰褰㈠紡 | 缍叉牸闄ｅ垪 |
鍒堕�犲晢鍖呰瑾槑 | 鐒￠墰锛孎(xi脿n)BGA-1152 |
鐒￠墰鐙�鎱�(t脿i)/RoHS鐙�鎱�(t脿i) | 鐒￠墰/绗﹀悎RoHS |
姘村垎鏁忔劅鎬ф按骞�(MSL) | 3(168灏忔檪) |
姣忚嚭瑷倷72,600鑷�813,050绛夋晥LE
鍙法绋嬮浕婧愭妧琛�锛屽彲鍦ㄦ渶澶х▼搴﹂檷浣庡姛鑰楃殑鍚屾檪鏈�澶у寲瑷倷鎬ц兘
鍙法绋嬬殑鐧�(f膩)灏勬闋愬姞閲嶅拰鎺ユ敹姗熷潎琛￠浕璺紝鍙鍎熺墿鐞嗕粙璩腑鑸囬牷鐜囨湁闂滅殑鎼嶈��
姣忓�嬭ō鍌欐渶澶�16鍊嬪叏灞�鏅傞悩(GCLK)锛�88鍊嬪崁(q奴)鍩熸檪閻�(RCLK)鍜�132鍊嬪鍦嶆檪閻�(PCLK)
姣忓�嬮�氶亾鐨勫吀鍨嬬墿鐞嗕粙璩檮浠�(PMA)鍔熻�楀垎鍒ョ偤3.125 Gbps鍜�100 mW锛�6.375 Gbps鏅傜偤135 mW
Stratix IV E鍣ㄤ欢鐨勫紩鑵虫帓鍒楋紝鏃ㄥ湪鍏佽ū灏囪ō瑷堝緸Stratix III 閬风Щ鍒癝tratix IV E锛岃�屽皪PCB鐨勫奖闊挎渶灏�
澶氶仈1,120鍊嬬敤鎴禝 / O寮曡叧甯冪疆鍦�24鍊嬫ā濉婂寲I / O bank涓�锛岄�欎簺妯″鏀寔寤ｆ硾鐨勫柈绔拰宸垎I / O妯欐簴
Stratix IV GX鍜孏T鍣ㄤ欢涓閬�48鍊嬪熀浜嶤DR鐨勫叏闆欏伐鏀剁櫦(f膩)鍣�锛屽垎鍒ユ敮鎸侀珮閬�8.5 Gbps鍜�11.3 Gbps鐨勬暩鎿氶�熺巼
鍏锋湁宓屽叆寮廝CIe纭琁P妯″鐨勫畬鏁碢CIe鍗�(xi茅)璀拌В姹烘柟妗�锛岄�欎簺妯″瀵︾従(xi脿n)PHY-MAC灞�锛屾暩鎿氶張璺堡鍜屼簨鍕欒檿鐞嗗堡鍔熻兘
7,370鑷�33,294 Kb鐨勫寮峰瀷TriMatrix瀛樺劜鍣紝鐢变笁绋甊AM 濉婂ぇ灏忕祫鎴�锛屽彲瀵︾従(xi脿n)鐪熸鐨勯洐绔彛瀛樺劜鍣ㄥ拰FIFO绶╂矕鍗�(q奴)
鍏锋湁涓茶鍣�/瑙ｄ覆鍣�(SERDES)锛屽嫊鎱�(t脿i)鐩镐綅灏嶆簴(DPA)鍜宻oft-CDR闆昏矾鐨勯珮閫烲VDS I / O鏀寔锛屾暩鎿氶�熺巼楂橀仈1.6 Gbps
鏀寔婧愬悓姝ョ附绶氭婧�锛屽寘鎷琒GMII锛孏bE锛孲PI-4 闅庢2(POS-PHY绱氬垾4)锛孲FI-4.1锛孹SBI锛孶TOPIA IV锛孨PSI鍜孋SIX-L1
楂橀�熸暩瀛椾俊铏熻檿鐞�(DSP)妯″锛屾渶楂樺彲閰嶇疆鐐�9 x 9浣�锛�12 x 12浣嶏紝18 x 18浣嶅拰36 x 36浣嶅叏绮惧害涔樻硶鍣�锛屾渶楂橀牷鐜囩偤600 MHz
鎸佸閬�24鍊嬫ā濉婂寲I / O bank 涓婄殑楂橀�熷閮ㄥ瓨鍎插櫒鎺ュ彛锛屽寘鎷珼DR锛孌DR2锛孌DR3 SDRAM锛孯LDRAM II锛孮DR II鍜孮DR II + SRAM
灏堢敤闆昏矾鍙敮鎸佹祦琛屼覆琛屽崝(xi茅)璀扮殑鐗╃悊灞ゅ姛鑳�锛屼緥濡侾CI Express(PCIe)(PIPE)Gen1鍜孏en2锛孏bps浠ュお缍�(GbE)锛屼覆琛孯apidIO锛孲ONET / SDH锛孹AUI / HiGig锛�(OIF)CEI-6G 锛孲D / HD / 3G-SDI锛屽厜绾栭�氶亾锛孲FI-5鍜孖nterlaken
EP4SGX110HF35C3N绗﹁櫉
EP4SGX110HF35C3N鑵冲嵃
