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EP4SGX180FF35C3N 鏄竴娆剧敱鑻辩壒鐖撅紙Intel锛夌敓鐢�(ch菐n)鐨� Stratix IV GX 绯诲垪鐨� FPGA 鑺墖銆傝┎绯诲垪鑺墖灏堢偤楂樻�ц兘鍜岄珮瀵嗗害鎳夌敤瑷▓锛岄仼鐢ㄤ簬閫氫俊銆佺恫(w菐ng)绲°�佽粛浜�銆佽埅绌鸿埅澶╃瓑闋樺煙銆�
銆�銆�Stratix IV GX 鍩轰簬 40nm 宸ヨ棟鎶�琛撳埗閫�锛屾敮鎸侀珮閫熶覆琛屾敹鐧�(f膩)鍣ㄥ姛鑳�锛岃兘澶犳彁渚涘崜瓒婄殑绯荤当(t菕ng)甯跺鍜屾�ц兘銆侲P4SGX180FF35C3N 鍏锋湁璞愬瘜鐨勯倧杓硣婧愬拰宓屽叆寮忓瓨鍎插櫒濉�锛岄仼鍚堣檿鐞嗗京闆滅殑鏁�(sh霉)鎿�(j霉)娴佸拰淇¤櫉铏曠悊浠诲嫏銆�
鍨嬭櫉锛欵P4SGX180FF35C3N
銆�銆�鍝佺墝锛欼ntel
銆�銆�绯诲垪锛歋tratix IV GX
銆�銆�宸ヨ棟鍒剁▼锛�40nm
銆�銆�I/O 鏁�(sh霉)閲忥細916
銆�銆�閰嶇疆闁冨瓨锛氫笉鍏�(n猫i)缃�
銆�銆�鍏�(n猫i)鏍搁浕澹擄細1.0V
銆�銆�灏佽椤炲瀷锛欶BGA
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 180K
銆�銆�鏀剁櫦(f膩)鍣ㄩ�氶亾鏁�(sh霉)锛�36
銆�銆�鏈�澶х敤鎴� I/O 寮曡叧锛�916
EP4SGX1 鎻愪緵浜嗛珮鎬ц兘鐨勫彲绶ㄧ▼閭忚集鑳藉姏浠ュ強闈堟椿鐨� I/O 閰嶇疆閬搁爡銆傚叾涓昏鐗归粸鍖呮嫭锛�
銆�銆�1. 鏀寔楂橀仈 11.3 Gbps 鐨勬敹鐧�(f膩)鍣ㄩ�熺巼锛屾豢瓒抽珮閫熸暩(sh霉)鎿�(j霉)鍌宠几闇�姹�銆�
銆�銆�2. 鍏�(n猫i)閮ㄩ泦鎴愪簡澶у閲忕殑宓屽叆寮� RAM 鍜� DSP 妯″锛岃兘澶犲劒(y艒u)鍖栨暩(sh霉)鎿�(j霉)瀛樺劜鍜岃檿鐞嗘�ц兘銆�
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銆�銆�4. 鏀寔澶氱ó鏅傞悩绠＄悊鎶�琛�锛屽 PLL 鍜� DPLL锛岀⒑淇濈簿纰虹殑鏅傞悩鍒嗛厤鑸囧悓姝�銆�
銆�銆�5. 鎻愪緵楂樼礆鐨勫畨鍏ㄧ壒鎬э紝渚嬪 AES 鍔犲瘑鍜屽熀浜庣‖浠剁殑淇′换鏍逛繚璀�锛屼互闃叉鎯℃剰鏀绘搳鍜岄�嗗悜宸ョ▼銆�
銆�銆�6. 鏀寔涓绘祦鐨勬帴鍙ｆ婧�锛屽寘鎷� PCIe Gen3銆乆AUI 鍜� CPRI锛岀啊鍖栫郴绲�(t菕ng)闆嗘垚銆�
瑭� FPGA 鑺墖寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 閫氫俊鍩虹瑷柦锛氬鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙涓殑淇¤櫉铏曠悊銆�
銆�銆�2. 楂樻�ц兘瑷堢畻锛氱敤浜庣瀛歌▓绠�銆佸ぇ鏁�(sh霉)鎿�(j霉)鍒嗘瀽鍜屾鍣ㄥ缈掓帹鐞嗗姞閫�銆�
銆�銆�3. 杌嶄簨鑸囪埅绌鸿埅澶╋細闆烽仈銆佽(w猫i)鏄熼�氫俊鍜屽皫鑸郴绲�(t菕ng)鐨勫鏅傛暩(sh霉)鎿�(j霉)铏曠悊銆�
銆�銆�4. 閱�(y墨)鐧傛垚鍍忥細CT 鎺冩弿鍎�銆丮RI 瑷倷涓殑鍦栧儚閲嶅缓绠楁硶瀵︾従(xi脿n)銆�
銆�銆�5. 瑕栭牷铏曠悊锛氳闋荤法纰艰В纰�銆佸湒鍍忓寮风瓑浠诲嫏銆�
EP4SGX230KF40C2, EP4SGX230KF40I2
