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銆€銆€閫欐 FPGA 閰嶅倷浜嗚睈瀵岀殑 DSP 妯″銆佸祵鍏ュ紡瀛樺劜鍣ㄥ浠ュ強楂橀€熸敹鐧�(f膩)鍣�锛屾敮鎸佸绋崝(xi茅)璀板拰鎺ュ彛妯�(bi膩o)婧�(zh菙n)銆傛澶栵紝瀹冮倓闆嗘垚浜嗘暩(sh霉)瀛楁檪(sh铆)閻樼鐞嗘ā濉婏紙DCM锛�锛屽彲浠ュ(sh铆)鐝�(xi脿n)闈堟椿鐨勬檪(sh铆)閻樼鐞嗗拰鐩镐綅瑾�(di脿o)鏁淬€�

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鍨嬭櫉锛欵P4SGX530HH35I3N
銆€銆€鍝佺墝锛欼ntel
銆€銆€绯诲垪锛歋tratix IV GX
銆€銆€宸ヨ棟锛�65nm
銆€銆€閭忚集鍠厓鏁�(sh霉)閲忥細绱� 53 钀�
銆€銆€RAM 濉婂閲忥細12.7Mb
銆€銆€DSP 妯″鏁�(sh霉)閲忥細780
銆€銆€IO 寮曡叧鏁�(sh霉)锛�912
銆€銆€閰嶇疆妯″紡锛欰S 鍜� JTAG
銆€銆€宸ヤ綔闆诲锛�1.0V 鏍稿績闆诲 / 2.5V IO 闆诲
銆€銆€灏佽椤炲瀷锛欶FG900
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C

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銆€銆€1. 楂樻€ц兘鏋舵(g貌u)锛氶噰鐢� 65nm 宸ヨ棟鍒堕€�锛屾敮鎸侀珮閬�(d谩) 53 钀€�(g猫)閭忚集鍠厓锛岄仼鍚堝京(f霉)闆滆ō(sh猫)瑷�(j矛)闇€姹�銆�
銆€銆€2. 鍏�(n猫i)缃‖鏍� IP锛氭敮鎸� PCI Express銆佸崈鍏嗕互澶恫(w菐ng) MAC 鍜� RocketIO 鏀剁櫦(f膩)鍣ㄧ瓑鍔熻兘銆�
銆€銆€3. 楂橀€熶覆琛屾敹鐧�(f膩)鍣細鏈€楂樺彲閬�(d谩) 11.3 Gbps 鐨勫偝杓搁€熺巼锛岄仼鐢ㄤ簬澶氱ó楂橀€熸帴鍙ｅ崝(xi茅)璀般€�
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