LC4064V-25TN100-5I 鏅傞枔锛�2025/4/27 11:37:47 闁辫畝锛�31

LC4064V-25TN100-5I 鏄竴娆剧敱 IDT锛圛ntegrated Device Technology锛夊叕鍙哥敓鐢�(ch菐n)鐨勪綆鍔熻€�銆侀珮绮惧害鐨� 64K x 8 (512Kb) CMOS 闈滄厠(t脿i)闅ㄦ瀛樺彇瀛樺劜鍣紙SRAM锛�銆傝┎鑺墖閲囩敤鍏堥€茬殑 CMOS 宸ヨ棟鍒堕€狅紝鍏峰倷蹇€熻í鍟忔檪闁�銆佷綆鍔熻€楀拰楂樺彲闈犳€х瓑鐗规€�銆傚叾瑷�(sh猫)瑷堜富瑕佺敤浜庡皪閫熷害鍜岀┅(w臎n)瀹氭€ц姹傝純楂樼殑鎳�(y墨ng)鐢ㄥ牬鍚�銆�
銆€銆€LC4064V 绯诲垪 SRAM 鎻愪緵澶氱ó灏佽褰㈠紡锛屽叾涓� -25TN100 琛ㄧず瑭插櫒浠堕噰鐢� 100 寮曡叧 Thin Fine-Pitch Ball Grid Array (TFBGA) 灏佽锛屽伐浣滈牷鐜囬珮閬� 25 MHz锛岃兘澶犳豢瓒抽珮閫熸暩(sh霉)鎿�(j霉)铏曠悊闇€姹�銆�

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绲勭箶绲�(ji茅)妲�(g貌u)锛�64K x 8
銆€銆€瀛樺劜瀹归噺锛�512Kb
銆€銆€鏁�(sh霉)鎿�(j霉)瀵害锛�8 浣�
銆€銆€瑷晱鏅傞枔锛�4 ns
銆€銆€宸ヤ綔闆诲锛�1.7V 鑷� 1.9V
銆€銆€灏佽椤炲瀷锛�100 寮曡叧 TFBGA
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆€銆€寮曡叧閰嶇疆锛氱鍚� JEDEC 妯�(bi膩o)婧�(zh菙n)
銆€銆€闈滄厠(t脿i)闆绘祦锛�20 mA锛堝吀鍨嬪€硷級
銆€銆€鍕曟厠(t脿i)闆绘祦锛�30 mA锛堝吀鍨嬪€硷級

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LC4064V-25TN100-5I 鍏锋湁浠ヤ笅椤憲鐗归粸锛�
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