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闁辫畝锛�807
MK10DN512VLL10鏄竴娆惧熀浜嶢RMCortex-M4RISC鏋舵鍏ф牳鐨�32浣岾inetis K1x Baseline寰帶鍒跺櫒锛屾渶楂橀亱琛岄牷鐜囩偤100MHz銆傝┎鍣ㄤ欢鍖呭惈512kB鍏ч儴闁冨瓨銆�128kB鍏ч儴RAM銆佸叐鍊�16浣峉ARA/D杞夋彌鍣�銆佷竴鍊�12浣岲/A杞夋彌鍣ㄥ拰70鍊嬮�氱敤I/O寮曡叧銆傝┎鍣ㄤ欢閭勫叿鏈夐�氫俊鎺ュ彛锛屽浜斿�婾ART妯″銆佷笁鍊婼PI妯″銆佸叐鍊婭2C妯″鍜屼竴鍊婭2S妯″銆�
鐢�(ch菐n)鍝佸瀷铏� | MK10DN512VLL10 |
鎻忚堪 | IC MCU 32BIT 512KB闁冨瓨100LQFP |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-寰帶鍒跺櫒 |
鍒堕�犲晢 | 鎭╂櫤娴﹀崐灏庨珨 |
绯诲垪 | Kinetis K10 |
闆诲-闆绘簮(Vcc / Vdd) | 1.71V?3.6V |
宸ヤ綔婧害 | -40掳C?105掳C(TA) |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鍖呰/绠� | 100-LQFP |
渚涙噳鍟嗚ō鍌欏寘瑁� | 100-LQFP(14x14) |
鍩烘湰闆朵欢铏� | MK10DN512 |
MK10DN512VLL10
鐢�(ch菐n)鍝佸垎椤� | ARM寰帶鍒跺櫒-MCU |
绯诲垪 | K10_100 |
鏍稿績 | ARMCortexM4 |
绋嬪簭瀛樺劜鍣ㄥぇ灏� | 512KB |
鏁�(sh霉)鎿�(j霉)绺界窔瀵害 | 32浣� |
ADC鍒嗚鲸鐜� | 16浣� |
鏈�澶ф檪閻橀牷鐜� | 100鍏嗚但 |
鏁�(sh霉)鎿�(j霉)RAM澶у皬 | 128KB |
宸ヤ綔闆绘簮闆诲 | 3.3浼� |
绋嬪簭瀛樺劜鍣ㄩ鍨� | 闁冨厜 |
鎺ュ彛椤炲瀷 | CAN锛孲PI锛孖2C锛孶ART |
妯℃摤闆绘簮闆诲 | 3.3浼� |
杓稿叆/杓稿嚭闆诲 | 3.3浼� |
A/D杞夋彌鍣ㄦ暩(sh霉)閲� | 2 |
ADC閫氶亾鏁�(sh霉) | 2 |
I2C閫氶亾鏁�(sh霉) | 2 |
I/O鏁�(sh霉)閲� | 70 |
PWM閫氶亾鏁�(sh霉) | 8 |
SPI閫氶亾鏁�(sh霉) | 3 |
瑷堟檪鍣�/瑷堟暩(sh霉)鍣ㄦ暩(sh霉)閲� | 13 |
UART閫氶亾鏁�(sh霉) | 5 |
鎸暕鍣ㄩ鍨� | 鍏ч儴 |
楂樺害 | 1.7姣背 |
闀峰害 | 14姣背 |
瀵害 | 14姣背 |
鍖呰 | 鎵樼洡 |
瀹夎鏂瑰紡 | 璨肩墖/璨肩墖 |
鍖呰/绠� | LQFP-100 |
RoHS鐙�鎱�(t脿i) | 绗﹀悎ROHS3 |
姘村垎鏁忔劅鎬ф按骞�(MSL) | 3(168灏忔檪) |
鍏锋湁DSP鎸囦护鐨凙RMCortex-M4鍏ф牳锛屾瘡鍏嗚但鍙彁渚�1.25DhrystoneMIPS
涓茶绶ㄧ▼鎺ュ彛(EzPort)
3鑷�32MHz鏅堕珨鎸暕鍣�
澶氬姛鑳芥檪閻樼櫦(f膩)鐢熷櫒
澶氱ó浣庡姛鑰楁ā寮�锛屽彲鏍规摎(j霉)鎳夌敤闇�姹傛彁渚涘姛鐜囧劒(y艒u)鍖�
鍏锋湁澶氫富淇濊鍔熻兘鐨勫収瀛樹繚璀峰柈鍏�
16閫氶亾DMA鎺у埗鍣紝鏈�澶氭敮鎸�128鍊嬭珛姹傛簮
澶栭儴鐪嬮杸鐙楃洠(ji膩n)瑕栧櫒
杌熶欢鐪嬮杸鐙�
浣庢硠婕忓枤閱掑柈鍏�
纭欢CRC妯″鏀寔蹇�熷惊鐠�(hu谩n)鍐椾綑鏍￠
姣忓�嬭姱鐗�128浣嶅敮涓�妯欒瓨(ID)铏�
浣庡姛鑰楃‖浠惰Ц鎽稿偝鎰熷櫒鎺ュ彛(TSI)
闆嗘垚鍒版瘡鍊婣DC鐨勫彲绶ㄧ▼澧炵泭鏀惧ぇ鍣�(PGA)
鍏╁�嬩簰闃绘斁澶у櫒
涓夊�嬪寘鍚�6浣岲AC鍜屽彲绶ㄧ▼鍙冭�冭几鍏ョ殑妯℃摤姣旇純鍣�(CMP)
鍙冭�冮浕澹�
鍙法绋嬪欢閬插
8閫氶亾闆绘鎺у埗/閫氱敤/PWM瀹氭檪鍣�
鍏╁��2閫氶亾姝ｄ氦瑙ｇ⒓鍣�/閫氱敤瀹氭檪鍣�
MK10DN512VLL10绗﹁櫉
MK10DN512VLL10鑵冲嵃
MK10DN512VLL10灏佽
