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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > SY87700VSC

SY87700VSC 鐧�(f膩)甯冩檪闁� 鏅傞枔锛�2024/7/26 15:07:59 鏌ョ湅 闁辫畝锛�374

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3.3V鍜�5V闆绘簮閬搁爡
銆�銆�SONET/SDH/ATM鍏煎
銆�銆�鏅傞悩鍜屾暩(sh霉)鎿�(j霉)寰�32Mbps鎭㈠京(f霉)鍒�175Mbps NRZ鏁�(sh霉)鎿�(j霉)娴�锛屾檪閻樼敓鎴愬緸32Mbps鍒�175Mbps
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銆�銆�绶氳矾鎺ユ敹鍣ㄨ几鍏ワ細鐒￠渶澶栭儴绶╂矕
銆�銆�閺堣矾鏁呴殰鎸囩ず
銆�銆�100K ECL鍏煎I/O
銆�銆�绗﹀悎Bellcore銆両TU/CCCITT鍜孉NSI瑕�(gu墨)鑼�锛屽OC-1銆丱C-3銆丗DDI銆丗astEthernet浠ュ強灏堟湁鎳�(y墨ng)鐢�

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椤炲垾锛氶泦鎴愰浕璺� (IC)
銆�銆�瀹跺涵锛氭檪閻�/瑷堟檪 - 灏堢敤
銆�銆�椤炲瀷锛氭檪閻樺拰鏁�(sh霉)鎿�(j霉)鎭㈠京(f霉) (CDR)
銆�銆�杓稿叆锛歅ECL, TTL
銆�銆�杓稿嚭锛歅ECL, TTL
銆�銆�闋荤巼 - 鏈�澶э細1.25GHz
銆�銆�闆绘簮闆诲锛�3.15 V ~ 3.45 V, 4.75 V ~ 5.25 V
銆�銆�宸ヤ綔婧害锛�0鈩� ~ 85鈩�
銆�銆�瀹夎椤炲瀷锛氳〃闈㈣布瑁�
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銆�銆�渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細28-SOIC EPAD

sy87700vsc鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

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  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児

sy87700vsc鍙冩暩(sh霉)

  • 妯�(bi膩o)婧�(zh菙n)鍖呰54
  • 椤炲垾闆嗘垚闆昏矾 (IC)
  • 瀹跺涵鏅傞悩/瑷堟檪 - 灏堢敤
  • 绯诲垪AnyRate®
  • 椤炲瀷鏅傞悩鍜屾暩(sh霉)鎿�(j霉)鎭㈠京(f霉)锛圕DR锛�锛屽璺京(f霉)鐢ㄥ櫒
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  • 杓稿叆PECL
  • 杓稿嚭PECL
  • 闆昏矾鏁�(sh霉)1
  • 姣旂巼 - 杓稿叆:杓稿嚭1:3
  • 宸垎 - 杓稿叆:杓稿嚭鏄�/鏄�
  • 闋荤巼 - 鏈�澶�175Mbps
  • 闆绘簮闆诲3.15 V ~ 5.25 V
  • 宸ヤ綔婧害0°C ~ 85°C
  • 瀹夎椤炲瀷琛ㄩ潰璨艰
  • 灏佽/澶栨28-SOIC锛�0.295"锛�7.50mm 瀵級瑁搁湶鐒婄洡
  • 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�28-SOIC EPAD
  • 鍖呰鎵樼洡