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XA6SLX25T-3CSG324Q 鏄竴娆剧敱 Xilinx锛堣辰闈堟�濓級鎺ㄥ嚭鐨� Spartan-6 绯诲垪 FPGA 鑺墖銆係partan-6 FPGA 鏄熀浜� 45nm 宸ヨ棟鎶�琛撳埗閫犵殑楂樻�ц兘銆佷綆鎴愭湰鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪鑺墖锛岄仼鐢ㄤ簬閫氫俊銆佸伐妤�(y猫)鎺у埗銆佹秷璨婚浕瀛愬拰姹借粖绛夊鍊嬮牁鍩熴�俋A6SLX25T 鏄┎绯诲垪涓殑涓�娆惧皬鍨嬪寲鍣ㄤ欢锛屽叿鏈夎純浣庣殑閭忚集璩囨簮鍜岃睈瀵岀殑 I/O 鍔熻兘锛岄仼鍚堝皪鎴愭湰鏁忔劅鐨勬噳鐢ㄥ牬鏅�銆�
銆�銆�XA6SLX25T 鎻愪緵浜嗛潏娲荤殑纭欢鏋舵锛屽寘鎷彲閰嶇疆閭忚集濉婏紙CLB锛夈�佹暩(sh霉)瀛椾俊铏熻檿鐞嗭紙DSP锛夋ā濉�銆佸祵鍏ュ紡瀛樺劜鍣ㄥ浠ュ強澶氱ó纭牳鍜岃粺鏍稿瑷�傛澶�锛屽畠鏀寔澶氱ó涓茶鍜屽苟琛屾帴鍙ｆ婧栵紝鐐鸿ō瑷堣�呮彁渚涗簡妤靛ぇ鐨勯潏娲绘��銆�
鍨嬭櫉锛歑A6SLX25T-3CSG324Q
銆�銆�灏佽锛欳SG324
銆�銆�宸ヨ棟锛�45nm
銆�銆�鍏�(n猫i)鏍搁浕澹擄細1.2V
銆�銆�I/O 闆诲锛�1.8V / 2.5V / 3.3V
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細25,000
銆�銆�DSP Slice 鏁�(sh霉)閲忥細50
銆�銆�Block RAM锛�270Kb
銆�銆�閰嶇疆妯″紡锛歋lave Serial / Master Serial / SelectMAP
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
1. 楂樻�ц兘鑸囦綆鍔熻�楋細
銆�銆�XA6SLX25T 鍦ㄦ彁渚涢珮閭忚集瀵嗗害鐨勫悓鏅傚劒(y艒u)鍖栦簡鍕曟厠(t脿i)鍔熻�楀拰闈滄厠(t脿i)鍔熻��锛屼娇鍏堕潪甯搁仼鍚堥浕姹犱緵闆昏ō鍌欐垨灏嶆暎鐔辨湁鍤存牸瑕佹眰鐨勬噳鐢ㄣ��
銆�銆�2. 鍏�(n猫i)缃� DSP 妯″锛�
銆�銆�鍖呭惈澶氶仈 50 鍊� DSP Slice锛屾瘡鍊� Slice 鍙互瀵︾従(xi脿n)涔樻硶绱姞鎿嶄綔锛圡AC锛�锛岄仼鐢ㄤ簬淇¤櫉铏曠悊銆佹烤娉㈠櫒瑷▓绛変换鍕�銆�
銆�銆�3. 澶氱ó瀛樺劜鍣ㄩ伕闋咃細
銆�銆�闆嗘垚 270Kb 鐨勫垎甯冨紡鍜屽鐙� RAM锛屾敮鎸侀洐绔彛瑷晱鍜� FIFO 瀵︾従(xi脿n)銆�
銆�銆�4. 寮峰ぇ鐨� I/O 鏀寔锛�
銆�銆�鏀寔楂橀仈 324 鍊嬪紩鑵崇殑灏佽锛屽苟鍏煎澶氱ó闆诲钩妯欐簴锛屼緥濡� LVCMOS銆丩VDS 鍜� SSTL銆�
銆�銆�5. 澧炲挤鐨勫畨鍏ㄦ�э細
銆�銆�鏀寔 AES 128/256 浣嶅姞瀵嗗拰 CRC 閷妾㈡脯鍔熻兘锛岀⒑淇濋厤缃暩(sh霉)鎿�(j霉)鐨勫畨鍏ㄥ偝杓搞��
銆�銆�6. 鍙潬鎬э細
銆�銆�缍�(j墨ng)閬庤蓟灏勭‖鍖栬檿鐞�锛岄仼鍚堣埅绌鸿埅澶╁強妤电鐠�(hu谩n)澧冩噳鐢�銆�
XA6SLX25T-3CSG324Q 涓昏鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 宸ユキ(y猫)鑷嫊鍖栵細鐢ㄤ簬瀵︽檪鎺у埗銆佸偝鎰熷櫒鎺ュ彛鍜屾暩(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)銆�
銆�銆�2. 閫氫俊瑷倷锛氬鐝�(xi脿n)鍗�(xi茅)璀拌綁鎻�銆佷俊铏熻(di脿o)鐞嗗拰缍�(w菐ng)绲℃帴鍙ｅ姛鑳姐��
銆�銆�3. 娑堣不椤為浕瀛愮敘(ch菐n)鍝侊細濡傞珮娓呰闋昏檿鐞�銆佸湒褰㈠姞閫熷拰闊抽牷绶ㄧ⒓瑙ｇ⒓銆�
銆�銆�4. 閱�(y墨)鐧傝ō鍌欙細鏀寔閱�(y墨)鐧傛垚鍍�銆佹偅鑰呯洠(ji膩n)娓拰鍏朵粬渚挎敎寮忓仴搴疯ō鍌�銆�
銆�銆�5. 鑸┖鑸ぉ鑸囧湅闃诧細鍥犲叾鎶楄蓟灏勭壒鎬�锛屽彲鐢ㄤ簬琛�(w猫i)鏄熼�氫俊銆侀浄閬旂郴绲�(t菕ng)鍜屽皫鑸ō鍌�銆�
銆�銆�6. 姹借粖闆诲瓙锛氬鐝�(xi脿n)杌婅級濞涙▊绯荤当(t菕ng)銆侀珮绱氶椐涜紨鍔╋紙ADAS锛夌瓑鍔熻兘銆�
XA6SLX9T-3CSG324Q
銆�銆�XA6SLX16T-3CSG324Q
銆�銆�XA6SLX45T-3CSG324Q
