XA6SLX75-2FGG484Q 鏅�(sh铆)闁擄細2025/5/10 14:30:33 闁辫畝锛�27

XA6SLX75-2FGG484Q 鏄� Xilinx 鍏徃鐢熺敘(ch菐n)鐨� Spartan-6 绯诲垪 FPGA 鑺墖銆係partan-6 绯诲垪灞簬浣庢垚鏈� FPGA 瀹舵棌锛岄仼鐢ㄤ簬鍚勭ó宓屽叆寮忓拰閫氫俊鎳�(y墨ng)鐢ㄣ€俋A6SLX75 鐗堟湰鏄┎绯诲垪涓殑涓€娆炬摯(ku貌)灞曟韩搴﹁寖鍦嶇敘(ch菐n)鍝�锛岃兘澶犲湪鏇村鐨勫伐浣滄韩搴﹁寖鍦嶅収(n猫i)绌�(w臎n)瀹氶亱(y霉n)琛�锛岄仼鍚堝伐妤�(y猫)銆佹苯杌婂拰鍏朵粬闇€瑕侀珮鍙潬鎬х殑鐠�(hu谩n)澧冦€�
銆€銆€姝よ姱鐗囬噰鐢� 484 寮曡叧鐨� FGG锛團ine-Pitch Ground Grid Array锛夊皝瑁�锛屽叿鏈夊挤(qi谩ng)澶х殑閭忚集璩囨簮銆佸祵鍏ュ紡瀛樺劜(ch菙)鍣ㄥ鍜� DSP 妯″锛岃兘澶犳豢瓒冲京(f霉)闆滄暩(sh霉)瀛椾俊铏�(h脿o)铏曠悊鍜屾帶鍒朵换鍕�(w霉)鐨勯渶姹�銆�

鍙冩暩(sh霉)

鍨嬭櫉(h脿o)锛歑A6SLX75-2FGG484Q
銆€銆€鍝佺墝锛歑ilinx
銆€銆€绯诲垪锛歋partan-6
銆€銆€灏佽椤炲瀷锛欶GGG (Fine Pitch Ground Grid Array)
銆€銆€寮曡叧鏁�(sh霉)锛�484
銆€銆€閭忚集鍠厓鏁�(sh霉)閲忥細75000
銆€銆€RAM 绺介噺锛�1144 Kb
銆€銆€DSP Slice 鏁�(sh霉)閲忥細160
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆€銆€閰嶇疆闁冨瓨锛氫笉鍏�(n猫i)缃�
銆€銆€闆绘簮闆诲 VCCINT锛�1.2V
銆€銆€IO 闆绘簮闆诲锛�1.8V, 2.5V, 3.3V
銆€銆€鏈€灏忓伐浣滈牷鐜囷細10 MHz
銆€銆€鏈€澶у伐浣滈牷鐜囷細500 MHz

鐗规€�

XA6SLX75-2FGG484Q 鎻愪緵浜嗚睈瀵岀殑鍙法绋嬮倧杓硣婧愶紝鍖呮嫭 CLB锛圕onfigurable Logic Blocks锛�銆丅lock RAM 鍜� DSP Slices銆傚叾瑷�(sh猫)瑷�(j矛)鏀寔澶氱ó楂樻€ц兘鎺ュ彛妯�(bi膩o)婧�(zh菙n)锛屽 Gigabit Transceivers銆丳CI Express 鍜屽崈鍏嗕互澶恫(w菐ng) MAC銆傛澶�锛屽畠閭勯泦鎴愪簡 DCM锛圖igital Clock Manager锛夊拰 PLL锛圥hase-Locked Loop锛夛紝鍙互闈堟椿鐢熸垚鏅�(sh铆)閻樹俊铏�(h脿o)銆�
銆€銆€Spartan-6 绯诲垪鐗瑰垾娉ㄩ噸鍔熻€楀劒(y艒u)鍖�锛岄€氶亷(gu貌) Power-over-Ethernet 鎶€琛�(sh霉)锛岃兘澶犻’钁楅檷浣庣郴绲�(t菕ng)鏁撮珨鑳借€�銆傚悓鏅�(sh铆)锛岃┎鍣ㄤ欢鏀寔閮ㄥ垎閲嶆柊閰嶇疆鍔熻兘锛屽厑瑷卞嫊(d貌ng)鎱�(t脿i)鏇存柊鍏�(n猫i)閮ㄩ倧杓�锛屽緸鑰屾彁鍗囩郴绲�(t菕ng)鐨勯潏娲绘€у拰鏁堢巼銆�
銆€銆€鐢变簬鍏舵摯(ku貌)灞曟韩搴﹁寖鍦嶇殑鑳藉姏锛岄€欐 FPGA 闈炲父閬╁悎鐢ㄤ簬鎯″姡鐠�(hu谩n)澧冧笅鐨勫伐妤�(y猫)鑷嫊(d貌ng)鍖�銆侀啱(y墨)鐧傝ō(sh猫)鍌欎互鍙婅粛浜嬮€氫俊绛夊牬(ch菐ng)鏅€�

鎳�(y墨ng)鐢�

XA6SLX75-2FGG484Q 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬澶氬€�(g猫)闋�(l菒ng)鍩燂細
銆€銆€1. 宸ユキ(y猫)鎺у埗锛氬鍙法绋嬮倧杓帶鍒跺櫒锛圥LC锛夊拰宸ユキ(y猫)姗�(j墨)鍣ㄤ汉涓殑閬�(y霉n)鍕�(d貌ng)鎺у埗銆�
銆€銆€2. 宓屽叆寮忚瑕猴細鍖呮嫭姗�(j墨)鍣ㄨ瑕烘敐鍍忛牠鍜岃闋荤洠(ji膩n)鎺х郴绲�(t菕ng)銆�
銆€銆€3. 閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂斤細濡傚熀绔欓仩(yu菐n)绋嬪皠闋诲柈鍏冨拰灏忓瀷铚傜缍�(w菐ng)绲�(lu貌)銆�
銆€銆€4. 閱�(y墨)鐧傞浕瀛愶細渚嬪瓒呰伈娉㈡垚鍍忚ō(sh猫)鍌欏拰鐥呬汉鐩�(ji膩n)璀�(h霉)鍎€銆�
銆€銆€5. 姹借粖闆诲瓙锛氬彲鐢ㄤ簬楂樼礆(j铆)椐曢杓斿姪绯荤当(t菕ng)锛圓DAS锛夊拰杌婅級淇℃伅濞涙▊(l猫)绯荤当(t菕ng)銆�
銆€銆€6. 娑堣不(f猫i)椤為浕瀛愮敘(ch菐n)鍝侊細鏀寔澶氬獟楂旀挱鏀惧櫒鍜屾父鎴叉(j墨)涓殑鍦栧舰铏曠悊鍔熻兘銆�