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鍨嬭櫉锛歑A7A50T-1CSG325Q
銆�銆�绯诲垪锛欰rtix-7
銆�銆�鍝佺墝锛歑ilinx (AMD)
銆�銆�宸ヨ棟锛�28nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 50,000
銆�銆�RAM 瀹归噺锛�2.3 Mb
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銆�銆�I/O 寮曡叧鏁�(sh霉)閲忥細256
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銆�銆�灏佽褰㈠紡锛欳SG (Ceramic Flip-Chip Ball Grid Array)
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銆�銆�- 鍙厤缃殑 I/O 妯欐簴锛屽吋瀹� LVCMOS銆丩VDS 绛夊绋帴鍙ｅ崝(xi茅)璀�銆�
銆�銆�- 鍏х疆 PLL 鍜� MMCM 妯″锛屾敮鎸侀潏娲荤殑鏅傞悩绠＄悊銆�
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XA7A50T-1CSG325Q 寤ｆ硾鎳夌敤浜庨渶瑕侀珮鎬ц兘鍜岄潏娲绘�х殑闋樺煙锛屽叿楂斿寘鎷細
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銆�銆�- 宸ユキ(y猫)鎺у埗鍜岃嚜鍕曞寲瑷倷涓殑瀵︽檪鏁�(sh霉)鎿�(j霉)閲囬泦鑸囪檿鐞嗐��
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銆�銆�- 娑堣不闆诲瓙鐢㈠搧涓殑鍦栧舰鍔犻�熷拰瑕栭牷绶ㄨВ纰笺��
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XA7A35T-1CSG325Q
銆�銆�XA7A100T-1CSG325Q
銆�銆�XC7A50T-1CSG324I
