XC2V1000-5FGG256I 鏅傞枔锛�2022/11/2 16:25:19 闁辫畝锛�547

鐢�(ch菐n)鍝佸瀷铏�	XC2V1000-5FGG256I
鎻忚堪	IC FPGA 172 I/O 256FBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)

姒傝堪

鐢�(ch菐n)鍝佸瀷铏�	XC2V1000-5FGG256I
鎻忚堪	IC FPGA 172 I/O 256FBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)

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妤�(y猫)鐣岄鍊嬪钩鑷篎PGA瑙ｆ焙鏂规

IP娌夋蹈寮忔灦妲�(g貌u)

瀵嗗害寰�40K鍒�8M绯荤当(t菕ng)闁€

420 MHz鍏�(n猫i)閮ㄦ檪閻橀€熷害(楂樼礆鏁�(sh霉)鎿�(j霉))

840+ Mb / s I / O(楂樼礆鏁�(sh霉)鎿�(j霉))

SelectRAM鍏�(n猫i)瀛樺堡娆＄祼(ji茅)妲�(g貌u)

鍦�18 Kbit濉奡electRAM璩囨簮涓殑3 Mb闆欑鍙AM

楂橀仈1.5 Mb鐨勫垎甯冨紡SelectRAM璩囨簮

澶栭儴瀛樺劜鍣ㄧ殑楂樻€ц兘鎺ュ彛

DRAM鎺ュ彛路SDR / DDR SDRAM路缍�(w菐ng)绲�(lu貌)FCRAM路娓涘皯寤堕伈DRAM

SRAM鎺ュ彛路SDR / DDR SRAM路QDRSRAM

CAM鎺ュ彛

绠楄(sh霉)鍑芥暩(sh霉)

灏堢敤鐨�18浣峹 18浣嶄箻娉曞櫒妯″

蹇€熷墠鐬绘壙杓夐倧杓張

闈堟椿鐨勯倧杓硣婧�

鍏锋湁鏅傞悩浣胯兘鍔熻兘鐨勯珮閬�93,184鍊嬪収(n猫i)閮ㄥ瘎瀛樺櫒/閹栧瓨鍣�

楂橀仈93,184鍊嬫煡鎵捐〃(LUT)鎴栧彲绱氳伅(li谩n)鐨�16浣嶇Щ浣嶅瘎瀛樺櫒

瀵璺京(f霉)鐢ㄥ櫒鍜屽杓稿叆鍔熻兘鏀寔

姗悜绱氳伅(li谩n)閺堝拰鐢�(ch菐n)鍝佺附鍜屾敮鎸�

鍏�(n猫i)閮ㄤ笁鎱�(t脿i)鍖祦

楂樻€ц兘鏅傞悩绠＄悊闆昏矾

鏈€澶�12鍊婦CM(鏁�(sh霉)瀛楁檪閻樼鐞嗗櫒)妯″路绮剧⒑鐨勬檪閻樻牎姝Ｂ烽潏娲荤殑闋荤巼鍚堟垚路楂樺垎杈ㄧ巼鐩哥Щ

16鍊嬪叏灞€鏅傞悩澶氳矾寰�(f霉)鐢ㄧ珐娌栧櫒

鏈夋簮浜掗€ｆ妧琛�(sh霉)

绗洓浠ｅ垎娈佃矾鐢辩祼(ji茅)妲�(g貌u)

鍙爯(y霉)娓殑蹇€熻矾鐢卞欢閬�锛岀崹绔嬩簬鎵囧嚭

SelectIO - 瓒呯礆鎶€琛�(sh霉)

鏈€澶�1,108鍊嬬敤鎴禝 / O.

19鍊嬪柈绔拰6鍊嬪樊鍒嗘婧�

姣忓€婭 / O鍙法绋嬬亴闆绘祦(2 mA鑷�24 mA)

鏁�(sh霉)瀛楁帶鍒堕樆鎶�(DCI)I / O锛氱敤浜庡柈绔疘 / O妯欐簴鐨勭墖鍏�(n猫i)鍖归厤闆婚樆

鍏煎PCI-X(133 MHz鍜�66 MHz)锛�3.3V

绗﹀悎PCI妯欐簴(66 MHz鍜�33 MHz)锛�3.3V

绗﹀悎CardBus妯欐簴(33 MHz)锛�3.3V

宸垎淇¤櫉路鍏锋湁闆绘祦妯″紡椹�(q奴)鍕曞櫒鐨�840 Mb / s浣庡宸垎淇¤櫉I / O(LVDS)路绺界窔LVDS I / O路甯舵湁闆绘祦椹�(q奴)鍕曠珐娌栧櫒鐨勯杻闆绘暩(sh霉)鎿�(j霉)鍌宠几(LDT)I / O路浣庡姝ｇ櫦(f膩)灏勬サ鑰﹀悎閭忚集(LVPECL)I / O路鍏�(n猫i)缃瓺DR杓稿叆鍜岃几鍑哄瘎瀛樺櫒

灏堟湁鐨勯珮鎬ц兘SelectLink鎶€琛�(sh霉)路楂樺付瀵暩(sh霉)鎿�(j霉)璺緫路闆欏€嶆暩(sh霉)鎿�(j霉)閫熺巼(DDR)閺堟帴路鍩轰簬Web鐨凥DL鐢熸垚鏂规硶

鐢盭ilinx Foundation鍜孉lliance Series闁嬬櫦(f膩)绯荤当(t菕ng)鎻愪緵鏀寔

闆嗘垚鐨刅HDL鍜孷erilog瑷�(sh猫)瑷堟祦绋�

10M绯荤当(t菕ng)闁€瑷�(sh猫)瑷堢殑鍖法

浜掕伅(li谩n)缍�(w菐ng)鍦橀殜瑷�(sh猫)瑷�(ITD)宸ュ叿

鍩轰簬SRAM鐨勭郴绲�(t菕ng)鍏�(n猫i)閰嶇疆

蹇€烻electMAP閰嶇疆

涓夐噸鏁�(sh霉)鎿�(j霉)鍔犲瘑妯欐簴(DES)瀹夊叏閬搁爡(姣旂壒娴佸姞瀵�)

IEEE 1532鏀寔

閮ㄥ垎閲嶆柊閰嶇疆

鐒￠檺鐨勫彲閲嶇法绋嬫€�

鍥炶畝鍔熻兘

閲囩敤0.12渭m楂橀€熸櫠楂旂鐨�0.15渭m8灞ら噾灞伐钘�

1.5V(VCCINT)鍏�(n猫i)鏍搁浕婧愶紝灏堢敤3.3V VCCAUX杓斿姪鍜孷CCO I / O闆绘簮

IEEE 1149.1鍏煎鐨勯倞鐣屾巸鎻忛倧杓敮鎸�

閲囩敤涓夌ó妯欐簴绮剧窗闁撹窛(0.80 mm锛�1.00 mm鍜�1.27 mm)鐨勫€掕鑺墖鍜屽紩绶氶嵉鍚堢悆鏌甸櫍鍒�(BGA)灏佽

100%宸ュ粻娓│

鍙冩暩(sh霉)

鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
绗﹀悎姝愮洘RoHS妯欐簴	鏄�
鐙€鎱�(t脿i)	鍋滅敘(ch菐n)
鏅傞悩闋荤巼-鏈€澶у€�	750.0 MHz
CLB-Max鐨勭祫鍚堝欢閬�	0.39 ns
JESD-30浠ｇ⒓	S-PBGA-B256
JESD-609浠ｇ⒓	E1
CLB鏁�(sh霉)閲�	1280.0
绛夋晥闁€鏁�(sh霉)	1000000.0
杓稿叆鏁�(sh霉)閲�	172.0
閭忚集鍠厓鐨勬暩(sh霉)閲�	11520.0
杓稿嚭鏁�(sh霉)閲�	172.0
绲傜鏁�(sh霉)閲�	256
RAM澶у皬	7815168 b
閫熷害绛夌礆	1
绺絉AM浣嶆暩(sh霉)	737280
绲勭箶	1280 CLBS锛�1000000 GATES
钃嬭尐鏁�(sh霉)閲�	鐧捐惉
宄板€煎洖娴佹韩搴�(鈩�)	260
闆绘簮	1.5,1.5 / 3.3,3.3
璩囨牸鐙€鎱�(t脿i)	涓嶅悎鏍�
鍧愬Э楂樺害-鏈€澶�	2.0姣背
瀛愰鍒�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
闆绘簮闆诲	1.5 V
闆绘簮闆诲-鏈€灏忓€�	1.425 V
闆绘簮闆诲-鏈€澶у€�	1.575 V
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
绲傜瀹屾垚	閷�/閵€/閵�(Sn95.5Ag4.0Cu0.5)
绲傜琛ㄦ牸	鐞�
绲傜闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅傞枔@宄板€煎洖娴佹韩搴�-鏈€澶у€�(s)	涓夊崄
闀峰害	17.0姣背
瀵害	17.0姣背
鍖呰楂旀潗鏂�	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰９浠ｇ⒓	BGA
鍖呯瓑鍍逛唬纰�	BGA256,16X16,40
鍖呰褰㈢媭	寤ｅ牬
鍖呰棰ㄦ牸	缍�(w菐ng)鏍奸櫍鍒�
鍒堕€犲晢鍖呰瑾槑	17 X 17 MM锛�1 MM闁撹窛锛岀劇閴�锛孧O-034AAF-1锛孎(xi脿n)BGA-256