XC2V3000-4BG728I 鏅傞枔锛�2022/11/8 13:59:01 闁辫畝锛�898

鐢�(ch菐n)鍝佸瀷铏�	XC2V3000-4BG728I
鎻忚堪	IC FPGA 516 I/O 728MBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)

姒傝堪

鐢�(ch菐n)鍝佸瀷铏�	XC2V3000-4BG728I
鎻忚堪	IC FPGA 516 I/O 728MBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)
鐢熺敘(ch菐n)寤犲	Xilinx鍏徃
绯诲垪	Virtex?-II
閮ㄥ垎鐙€鎱�(t脿i)	閬庢檪鐨�
闆诲-闆绘簮	1.425V~1.575V
宸ヤ綔婧害	-40掳C~100掳C(TJ)
鍖�/绠�	728 BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘	728-MBGA(35x35)
鍩虹(ch菙)閮ㄤ欢铏�	XC2V3000

鐗规€�

IP娌夋蹈寮忔灦妲�(g貌u)

绠楄(sh霉)鍑芥暩(sh霉)

100%宸ュ粻娓│

闈堟椿鐨勯倧杓硣婧�

鏈夋簮浜掗€ｆ妧琛�(sh霉)

SelectIO-Ultra鎶€琛�(sh霉)

楂樻€ц兘鏅傞悩绠＄悊闆昏矾

鍩轰簬SRAM鐨勭郴绲�(t菕ng)鍏�(n猫i)閰嶇疆

SelectRAM鍏�(n猫i)瀛樺堡娆＄祼(ji茅)妲�(g貌u)

澶栭儴瀛樺劜鍣ㄧ殑楂樻€ц兘鎺ュ彛

妤�(y猫)鐣岄鍊嬪钩鑷篎PGA瑙ｆ焙鏂规

閲囩敤鐒￠墰灏佽鐨勭窔鐒夿GA鍣ㄤ欢

IEEE 1149.1鍏煎閭婄晫鎺冩弿閭忚集鏀寔

0.15渭m8灞ら噾灞伐钘�锛�0.12渭m楂橀€熸櫠楂旂

鐢盭ilinx Foundation鍜孉lliance Series闁嬬櫦(f膩)绯荤当(t菕ng)鎻愪緵鏀寔

1.5V(VCCINT)鏍稿績闆绘簮锛屽皥鐢�3.3V VCCAUX杓斿姪鍜孷CCO I / O闆绘簮

涓夌ó妯�(bi膩o)婧�(zh菙n)绮剧窗(x矛)闁撹窛(0.80 mm锛�1.00 mm鍜�1.27 mm)鐨勫€掕鑺墖鍜屽紩绶氶嵉鍚堢悆鏌甸櫍鍒�(BGA)灏佽

鍙冩暩(sh霉)

鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
绗﹀悎REACH妯�(bi膩o)婧�(zh菙n)	鏄�
鐙€鎱�(t脿i)	鍋滅敘(ch菐n)
鏅傞悩闋荤巼-鏈€澶у€�	650.0 MHz
CLB-Max鐨勭祫鍚堝欢閬�	0.44 ns
JESD-30浠ｇ⒓	S-PBGA-B728
JESD-609浠ｇ⒓	E0
绺絉AM浣嶆暩(sh霉)	1769472
CLB鏁�(sh霉)閲�	3584.0
绛夋晥闁€鏁�(sh霉)	3000000.0
杓稿叆鏁�(sh霉)閲�	516.0
閭忚集鍠厓鐨勬暩(sh霉)閲�	32256.0
杓稿嚭鏁�(sh霉)閲�	516.0
绲傜鏁�(sh霉)閲�	728
绲勭箶	3584 CLBS锛�3000000 GATES
宄板€煎洖娴佹韩搴�(鈩�)	225
闆绘簮	1.5,1.5 / 3.3,3.3
璩囨牸鐙€鎱�(t脿i)	涓嶅悎鏍�
鍧愬Э楂樺害-鏈€澶�	2.6姣背
瀛愰鍒�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
闆绘簮闆诲	1.5 V
闆绘簮闆诲-鏈€灏忓€�	1.425 V
闆绘簮闆诲-鏈€澶у€�	1.575 V
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
绲傜瀹屾垚	閷�/閴�(Sn63Pb37)
绲傜琛ㄦ牸	鐞�
绲傜闁撹窛	1.27姣背
绲傜浣嶇疆	1.27姣背
绲傜浣嶇疆	搴曢儴
鏅傞枔@宄板€煎洖娴佹韩搴�-鏈€澶у€�(s)	涓夊崄
闀峰害	35.0姣背
瀵害	35.0姣背
鍖呰楂旀潗鏂�	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰９浠ｇ⒓	BGA
鍖呯瓑鍍逛唬纰�	BGA728,27X27,50
鍖呰褰㈢媭	寤ｅ牬
鍖呰棰�(f膿ng)鏍�	缍�(w菐ng)鏍奸櫍鍒�
鍒堕€犲晢鍖呰瑾槑	35 X 35 MM锛�1.27 MM PITCH锛孧S-034BAR-1锛孊GA-728