XC3S1400AN-4FGG676I 鏅�(sh铆)闁擄細2022/11/1 17:06:35 闁辫畝锛�919

鐢�(ch菐n)鍝佸瀷铏�(h脿o)	XC3S1400AN-4FGG676I
鎻忚堪	闆嗘垚闆昏矾FPGA 502 I / O 676FBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪)

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鐢�(ch菐n)鍝佸瀷铏�(h脿o)	XC3S1400AN-4FGG676I
鎻忚堪	闆嗘垚闆昏矾FPGA 502 I / O 676FBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪)
鍒堕€犲晢	Xilinx鍏徃
绯诲垪	Spartan?-3AN
鎵撳寘	鎵樼洡
闆朵欢鐙€鎱�(t脿i)	娲绘€�
闆诲-闆绘簮	1.14V1.26V
宸ヤ綔婧害	-40掳C100掳C(TJ)
鍖呰/绠�	676-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�	676-FBGA(27x27)
鍩烘湰闆朵欢铏�(h脿o)	XC3S1400AN

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姣忓€�(g猫)宸垎I/O640+Mb/s鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼

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DDR/DDR2SDRAM鏀寔楂橀仈(d谩)400Mb/s

瀹屽叏鍏煎32/64浣嶏紝33/66MHzPCI鎶€琛�(sh霉)鏀寔

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楂橀仈(d谩)176Kbit鐨勯珮鏁堝垎甯冨紡RAM

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鍙冩暩(sh霉)

鍒堕€犲晢鍖呰瑾�(shu艒)鏄�	FBGA-676
绗﹀悎REACH	鏄�
绗﹀悎姝愮洘RoHS	鏄�
鐙€鎱�(t脿i)	娲绘€�
鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪
鏈€澶ф檪(sh铆)閻橀牷鐜�	667.0鍏嗚但
CLB-Max鐨勭祫鍚堝欢閬�	0.71绱嶇
JESD-30浠ｇ⒓	S-PBGA-B676
JESD-609浠ｇ⒓	e1
绺絉AM浣�	589824
CLB鏁�(sh霉)閲�	2816.0
绛夋晥闁€鏁�(sh霉)	1400000.0
杓稿叆鏁�(sh霉)閲�	502.0
閭忚集鍠厓鏁�(sh霉)	25344.0
杓稿嚭鏁�(sh霉)閲�	408.0
绔瓙鏁�(sh霉)	676
鏈€浣庡伐浣滄韩搴�	-40鈩�
鏈€楂樺伐浣滄韩搴�	100鈩�
绲勭箶	2816 CLBS锛�1400000鍊�(g猫)闁€
鍖呰涓婚珨鏉愭枡	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰浠ｇ⒓	BGA
鍖呰绛夋晥浠ｇ⒓	BGA676,26X26,40
鍖呰褰㈢媭	鍥涙柟褰�
鍖呰褰㈠紡	缍�(w菐ng)鏍奸櫍鍒�
宄板€煎洖娴佹韩搴�(鈩�)	250
闆绘簮	1.2,1.2 / 3.3,3.3
搴ч珮	2.44姣背
瀛愰鍒�	鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪
闆绘簮闆诲妯�(bi膩o)绋�	1.2浼�
鏈€灏忎緵闆婚浕澹�	1.14浼�
鏈€澶ч浕婧愰浕澹�	1.26浼�
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
婧害绛夌礆(j铆)	鐢�(ch菐n)妤�(y猫)
绲傜瀹屾垚	閷�/閵€/閵�(Sn95.5Ag4.0Cu0.5)
绲傜琛ㄦ牸	鐞�
绔瓙闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅�(sh铆)闁揁宄板€煎洖娴佹韩搴�-鏈€澶�(绉�)	30
闀�(zh菐ng)搴�	27.0姣背
瀵害	27.0姣背