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鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XC4VLX100-10FF1148C

XC4VLX100-10FF1148C 鐧�(f膩)甯冩檪闁� 鏅傞枔锛�2023/8/7 16:32:12 鏌ョ湅 闁辫畝锛�392

鐢�(ch菐n)鍝佹杩�

鐢�(ch菐n)鍝佸瀷铏�
XC4VLX100-10FF1148C

鎻忚堪

IC,FPGA,VIRTEX-4,100K,1148-FBGA

鐢熺敘(ch菐n)寤犲

Xilinx鍏徃

绯诲垪

Virtex?-4 LX

闆诲 - 闆绘簮

1.14V~1.26V

宸ヤ綔婧害

0掳C~85掳C(TJ)

鍖�/绠�

1148-BBGA锛孎(xi脿n)CBGA

渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘

1148-FCPBGA(35x35)

鐢�(ch菐n)鍝佸湒鐗�

XC4VLX60-11FF1148C

XC4VLX100-10FF1148C

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍒堕�犲晢鍖呰瑾槑

1148-FCPBGA(35x35)

绗﹀悎REACH妯�(bi膩o)婧�(zh菙n)

鏄�

鐙�鎱�(t脿i)

娲绘��

鍙法绋嬮倧杓鍨�

鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪

鏅傞悩闋荤巼 - 鏈�澶у��

1028.0 MHz

JESD-30浠ｇ⒓

S-PBGA-B1148

JESD-609浠ｇ⒓

E0

CLB鏁�(sh霉)閲�

12288.0

杓稿叆鏁�(sh霉)閲�

768.0

閭忚集鍠厓鐨勬暩(sh霉)閲�

110592.0

杓稿嚭鏁�(sh霉)閲�

768.0

绲傜鏁�(sh霉)閲�

1148

宸ヤ綔婧害 - 鏈�灏忓��

0.0 Cel

宸ヤ綔婧害 - 鏈�楂�

85.0 Cel

绲勭箶

12288 CLBS

绺絉AM浣嶆暩(sh霉)

4423680

鍖呰楂旀潗鏂�

濉戞枡/鐠�(hu谩n)姘фü鑴�

鍖呰９浠ｇ⒓

BGA

鍖呯瓑鍍逛唬纰�

BGA1148,34X34,40

鍖呰褰㈢媭

寤ｅ牬

鍖呰棰�(f膿ng)鏍�

缍�(w菐ng)鏍奸櫍鍒�

宄板�煎洖娴佹韩搴�(Cel)

225

璩囨牸鐙�鎱�(t脿i)

涓嶅悎鏍�

鍧愬Э楂樺害 - 鏈�澶�

3.4姣背

瀛愰鍒�

鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪

闆绘簮闆诲

1.2 V

闆绘簮闆诲 - 鏈�灏忓��

1.14 V

闆绘簮闆诲 - 鏈�澶у��

1.26 V

琛ㄩ潰璨艰

鏄�

鎶�琛�(sh霉)

CMOS

婧害绛夌礆

鍏朵粬

绲傜瀹屾垚

閷�/閴�(Sn63Pb37)

绲傜琛ㄦ牸

鐞�

绲傜闁撹窛

1.0姣背

绲傜浣嶇疆

搴曢儴

闀峰害

35.0姣背

瀵害

35.0姣背

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

鐒￠墰鐙�鎱�(t脿i)/ RoHS鐙�鎱�(t脿i)

鍖呭惈閴�/ RoHS涓嶅悎瑕�(gu墨)

婵曞害鏁忔劅搴︾瓑绱�(MSL)

4(72灏忔檪)

CAD妯″瀷

XC4VLX60-11FF1148绗﹁櫉

XC4VLX60-11FF1148绗﹁櫉

XC4VLX60-11FF1148鑵冲嵃

XC4VLX60-11FF1148鑵冲嵃

xc4vlx100-10ff1148c鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�
  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児

xc4vlx100-10ff1148c鍦栫墖

xc4vlx100-10ff1148c

xc4vlx100-10ff1148c鐢�(ch菐n)鍝�