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鍨嬭櫉锛歑C4VLX15-12FFG668C
銆€銆€绯诲垪锛歏irtex-4 LX
銆€銆€鍒剁▼宸ヨ棟锛�90nm
銆€銆€FPGA 閭忚集鍠厓鏁�(sh霉)閲忥細绱� 1.5 钀€� Slice
銆€銆€閰嶇疆闁冨瓨锛氫笉鍏�(n猫i)缃�
銆€銆€I/O 鏁�(sh霉)閲忥細528
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C 鍟嗘キ(y猫)绱�
銆€銆€灏佽椤炲瀷锛欶FG668 (Fine Line BGA)
銆€銆€鏅傞悩闋荤巼锛氭渶楂橀€熷害绛夌礆鐐� -12锛屾敮鎸侀珮閬�(d谩) 550MHz 鐨勬€ц兘
銆€銆€鍏�(n猫i)宓屽瓨鍎插櫒锛氱磩 376KB 鍒嗗竷寮� RAM 鍜� 1440KB 濉婄媭 RAM (BRAM)
銆€銆€鍏�(n猫i)宓� DSP 妯″锛�24 鍊�
銆€銆€鍔熻€楋細鍏稿瀷鍊肩磩 4W

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