鏅傞枔锛�2022/11/4 16:29:02
闁辫畝锛�783
鐢�(ch菐n)鍝佸瀷铏� XC4VLX25-10FFG668I鎻忚堪IC FPGA 448 I/O 668FCBGA鍒嗛闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪)
鐢�(ch菐n)鍝佸瀷铏� XC4VLX25-10FFG668I鎻忚堪IC FPGA 448 I/O 668FCBGA鍒嗛闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪)鐢熺敘(ch菐n)寤犲Xilinx鍏徃绯诲垪Virtex?-4 LX閮ㄥ垎鐙�鎱�(t脿i)娲绘�ч浕澹�-闆绘簮1.14V~1.26V宸ヤ綔婧害-40掳C~100掳C(TJ)鍖�/绠�668-BBGA锛孎(xi脿n)CBGA渚涙噳鍟嗚ō鍌欏寘668-FCBGA(27x27)鍩虹閮ㄤ欢铏焁C4VLX25
Virtex-4 LX锛氶珮鎬ц兘閭忚集鎳夌敤瑙ｆ焙鏂规
Xesium鏅傞悩鎶�琛�(sh霉)
鏁�(sh霉)瀛楁檪閻樼鐞嗗櫒(DCM)濉�
闄勫姞鐨勭浉浣嶅尮閰嶆檪閻樺垎闋诲櫒(PMCD)
宸垎鍏ㄧ悆鏅傞悩
XtremeDSP鍒囩墖
18 x 18锛屼簩閫插埗瑁滅⒓锛屽付绗﹁櫉涔樻暩(sh霉)
鍙伕鐨勭閬撻殠
鍏�(n猫i)缃疮鍔犲櫒(48浣�)鍜屽姞娉曞櫒/娓涙硶鍣�
鏅鸿兘RAM鍏�(n猫i)瀛樺堡娆＄祼(ji茅)妲�(g貌u)
鍒嗗竷寮廟AM
闆欑鍙�18-Kbit RAM妯″路鍙伕娴佹按绶氱礆路鍙伕鐨勫彲绶ㄧ▼FIFO閭忚集鑷嫊灏嘡AM淇¤櫉閲嶆柊鏄犲皠鐐篎IFO淇¤櫉
楂橀�熷瓨鍎插櫒鎺ュ彛鏀寔DDR鍜孌DR-2 SDRAM锛孮DR-II鍜孯LDRAM-II
SelectIO鎶�琛�(sh霉)
1.5V鑷�3.3VI / O鎿嶄綔
鍏�(n猫i)缃瓹hipSync婧愬悓姝ユ妧琛�(sh霉)
鏁�(sh霉)瀛楁帶鍒堕樆鎶�(DCI)鏈夋簮绲傜
绮剧窗鐨処 / O閵�琛屾キ(y猫)鍕�(鍦ㄤ竴瀹堕妧琛岄厤缃�)
闈堟椿鐨勯倧杓硣婧�
瀹夊叏鑺墖AES姣旂壒娴佸姞瀵�
90 nm閵匔MOS宸ヨ棟
1.2V鏍稿績闆诲
鍊掕鑺墖灏佽鍖呮嫭鐒￠墰灏佽閬告搰
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
绗﹀悎REACH妯欐簴 | 鏄� |
绗﹀悎姝愮洘RoHS妯欐簴 | 鏄� |
鐙�鎱�(t脿i) | 娲绘�� |
鏅傞悩闋荤巼-鏈�澶у�� | 1028.0 MHz |
JESD-30浠ｇ⒓ | S-PBGA-B668 |
JESD-609浠ｇ⒓ | E1 |
绺絉AM浣嶆暩(sh霉) | 1327104 |
CLB鏁�(sh霉)閲� | 2688.0 |
杓稿叆鏁�(sh霉)閲� | 448.0 |
閭忚集鍠厓鐨勬暩(sh霉)閲� | 24192.0 |
杓稿嚭鏁�(sh霉)閲� | 448.0 |
绲傜鏁�(sh霉)閲� | 668 |
绲勭箶 | 2688 CLBS |
宄板�煎洖娴佹韩搴�(鈩�) | 245 |
璩囨牸鐙�鎱�(t脿i) | 涓嶅悎鏍� |
鍧愬Э楂樺害-鏈�澶� | 2.85姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲 | 1.2 V |
闆绘簮闆诲-鏈�灏忓�� | 1.14 V |
闆绘簮闆诲-鏈�澶у�� | 1.26 V |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛�(sh霉) | CMOS |
绲傜瀹屾垚 | 閷�/閵�/閵�(Sn95.5Ag4.0Cu0.5) |
绲傜琛ㄦ牸 | 鐞� |
绲傜闁撹窛 | 1.0姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅傞枔@宄板�煎洖娴佹韩搴�-鏈�澶у�� | 涓夊崄 |
闀峰害 | 27.0姣背 |
瀵害 | 27.0姣背 |
鍖呰楂旀潗鏂� | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰９浠ｇ⒓ | BGA |
鍖呯瓑鍍逛唬纰� | BGA668,26X26,40 |
鍖呰褰㈢媭 | 寤ｅ牬 |
鍖呰棰ㄦ牸 | 缍�(w菐ng)鏍奸櫍鍒� |
鍒堕�犲晢鍖呰瑾槑 | 鐒￠墰锛孎(xi脿n)BGA-668 |
