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鎮ㄥソ锛屾杩庝締(l谩i)鍒扮董搴�(k霉)闆诲瓙甯傚牬(ch菐ng)缍�(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺(c猫)

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩�(g貌u)缍�(w菐ng) > IC鐧剧 > XC4VLX40-10FF668I

XC4VLX40-10FF668I 鐧�(f膩)甯冩檪(sh铆)闁� 鏅�(sh铆)闁擄細2023/8/1 17:55:36 鏌ョ湅 闁辫畝锛�718

鐢�(ch菐n)鍝佹杩�

鐢�(ch菐n)鍝佸瀷铏�(h脿o)

XC4VLX40-10FF668I

鎻忚堪

闆嗘垚闆昏矾FPGA 448 I/O 668FCBGA

鍒嗛

闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪)

鍒堕�犲晢

Xilinx鍏徃

绯诲垪

Virtex?-4LX

鎵撳寘

鎵樼洡

闆朵欢鐙�鎱�(t脿i)

娲绘��

闆诲-闆绘簮

1.14V?1.26V

宸ヤ綔婧害

-40掳C?100掳C(TJ)

鍖呰/绠�

668-BBGA锛孎(xi脿n)CBGA

渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�

668-FCBGA(27x27)

鍩烘湰闆朵欢铏�(h脿o)

XC4VLX40

鐢�(ch菐n)鍝佸湒鐗�

XC4VLX40-10FF668I

XC4VLX40-10FF668I

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍙法绋嬮倧杓鍨�

鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪

绗﹀悎REACH

鏄�

鐙�鎱�(t脿i)

娲绘��

鏈�澶ф檪(sh铆)閻橀牷鐜�

1028.0鍏嗚但

JESD-30浠ｇ⒓

S-PBGA-B668

JESD-609浠ｇ⒓

00

绺絉AM浣�

1769472

CLB鏁�(sh霉)閲�

4608.0

杓稿叆鏁�(sh霉)閲�

448.0

閭忚集鍠厓鏁�(sh霉)

41472.0

杓稿嚭鏁�(sh霉)閲�

448.0

绔瓙鏁�(sh霉)

668

绲勭箶

4608 CLBS

宄板�煎洖娴佹韩搴�(鈩�)

225

璩囨牸鐙�鎱�(t脿i)

涓嶅悎鏍�

搴ч珮

2.85姣背

瀛愰鍒�

鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪

闆绘簮闆诲妯�(bi膩o)绋�

1.2浼�

鏈�灏忎緵闆婚浕澹�

1.14浼�

鏈�澶ч浕婧愰浕澹�

1.26浼�

瀹夎椤炲瀷

琛ㄩ潰璨艰

鎶�琛�(sh霉)

CMOS

绲傜瀹屾垚

閷�/閴�(Sn63Pb37)

绲傜琛ㄦ牸

鐞�

绔瓙闁撹窛

1.0姣背

绲傜浣嶇疆

搴曢儴

鏅�(sh铆)闁揁宄板�煎洖娴佹韩搴︽渶澶у��(绉�)

30

闀�(zh菐ng)搴�

27.0姣背

瀵害

27.0姣背

鍖呰涓婚珨鏉愭枡

濉戞枡/鐠�(hu谩n)姘фü鑴�

鍖呰浠ｇ⒓

BGA

鍖呰绛夋晥浠ｇ⒓

BGA668,26X26,40

鍖呰褰㈢媭

寤ｅ牬(ch菐ng)

鍖呰褰㈠紡

缍�(w菐ng)鏍奸櫍鍒�

鍒堕�犲晢鍖呰瑾�(shu艒)鏄�

FBGA-668

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

鐒�(w煤)閴涚媭鎱�(t脿i)/RoHS鐙�鎱�(t脿i)

鍖呭惈閴�/ RoHS涓嶅悎瑕�(gu墨)

姘村垎鏁忔劅鎬ф按骞�(MSL)

4(72灏忔檪(sh铆))

鐗归粸(di菐n)

?Virtex-4 LX锛氶珮鎬ц兘閭忚集鎳�(y墨ng)鐢ㄨВ姹烘柟妗�

?Xesium?鏅�(sh铆)閻樻妧琛�(sh霉)

銆傛暩(sh霉)瀛楁檪(sh铆)閻樼鐞嗗櫒(DCM)妯″

銆傞檮鍔犵殑鐩镐綅鍖归厤鏅�(sh铆)閻樺垎闋诲櫒(PMCD)

銆傚樊鍒嗗叏灞�鏅�(sh铆)閻�

?XtremeDSP?Slice

銆�18 x 18锛屼簩閫�(j矛n)鍒惰(b菙)纰�锛屽付绗﹁櫉(h脿o)涔樻硶鍣�

?锛熻泧x鐨勭閬撻殠娈�

銆傚収(n猫i)缃疮鍔犲櫒(48浣�)鍜屽姞娉曞櫒/娓涙硶鍣�

?鏅鸿兘RAM鍏�(n猫i)瀛樺堡娆＄祼(ji茅)妲�(g貌u)

銆傚垎甯冨紡RAM

銆傞洐绔彛18 Kbit RAM濉娐峰彲閬哥殑绠＄窔绱�(j铆)路鍙伕鐨勫彲绶ㄧ▼FIFO閭忚集鑷嫊(d貌ng)灏嘡AM淇¤櫉(h脿o)閲嶆柊鏄犲皠鐐篎IFO淇¤櫉(h脿o)

銆傞珮閫熷瓨鍎�(ch菙)鍣ㄦ帴鍙ｆ敮鎸丏DR鍜孌DR-2 SDRAM锛孮DR-II鍜孯LDRAM-II銆�

?SelectIO?鎶�琛�(sh霉)

銆�1.5V鑷�3.3VI / O鎿嶄綔

銆傚収(n猫i)缃瓹hipSync?婧愬悓姝ユ妧琛�(sh霉)

銆傛暩(sh霉)鎺ч樆鎶�(DCI)鏈夋簮绲傜

銆傜窗(x矛)绮掑害鐨処 / O閵�琛屾キ(y猫)鍕�(w霉)(鍦ㄤ竴鍊�(g猫)閵�琛屼腑閫�(j矛n)琛岄厤缃�)

?闈堟椿鐨勯倧杓硣婧�

?瀹夊叏鑺墖AES浣嶆祦鍔犲瘑

?90 nm閵匔MOS宸ヨ棟

?1.2V鏍稿績闆诲

?鍊掕鑺墖灏佽锛屽寘鎷劇(w煤)閴涘皝瑁濋伕鎿�

CAD妯″瀷

XC4VLX40-10FF668I绗﹁櫉(h脿o)

XC4VLX40-10FF668I绗﹁櫉(h脿o)

XC4VLX40-10FF668I鑵冲嵃

XC4VLX40-10FF668I鑵冲嵃

xc4vlx40-10ff668i鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�(h脿o)
  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉(h脿o)
  • 瑭㈠児(ji脿)

xc4vlx40-10ff668i鍦栫墖

xc4vlx40-10ff668i

xc4vlx40-10ff668i鍙冩暩(sh霉)

  • 妯�(bi膩o)婧�(zh菙n)鍖呰40
  • 椤炲垾闆嗘垚闆昏矾 (IC)
  • 瀹跺涵宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪锛�
  • 绯诲垪Virtex®-4 LX
  • LAB/CLB鏁�(sh霉)4608
  • 閭忚集鍏冧欢/鍠厓鏁�(sh霉)41472
  • RAM 浣嶇附瑷�(j矛)1769472
  • 杓稿叆/杓稿嚭鏁�(sh霉)448
  • 闁�鏁�(sh霉)-
  • 闆绘簮闆诲1.14 V ~ 1.26 V
  • 瀹夎椤炲瀷琛ㄩ潰璨艰
  • 宸ヤ綔婧害-40°C ~ 100°C
  • 灏佽/澶栨668-BBGA锛孎(xi脿n)CBGA
  • 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�668-FCBGA