XC4VLX60-11FF1148I 鏅�(sh铆)闁擄細2022/10/25 15:26:35 闁辫畝锛�544

鐢�(ch菐n)鍝佸瀷铏�(h脿o)XC4VLX60-11FF1148I鎻忚堪 IC FPGA 640 I/O 1148FCBGA鍒嗛闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)

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Xesium鏅�(sh铆)閻樻妧琛�(sh霉)

鏁�(sh霉)瀛楁檪(sh铆)閻樼鐞嗗櫒(DCM)濉�

闄勫姞鐨勭浉浣嶅尮閰嶆檪(sh铆)閻樺垎闋诲櫒(PMCD)

宸垎鍏ㄧ悆鏅�(sh铆)閻�

XtremeDSP鍒囩墖

18 x 18锛屼簩閫�(j矛n)鍒惰(b菙)纰硷紝甯剁铏�(h脿o)涔樻暩(sh霉)

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鍏�(n猫i)缃疮鍔犲櫒(48浣�)鍜屽姞娉曞櫒/娓涙硶鍣�

鏅鸿兘RAM鍏�(n猫i)瀛樺堡娆＄祼(ji茅)妲�(g貌u)

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闆欑鍙�18-Kbit RAM妯″路鍙伕娴佹按绶氱礆(j铆)路鍙伕鐨勫彲绶ㄧ▼FIFO閭忚集鑷嫊(d貌ng)灏嘡AM淇¤櫉(h脿o)閲嶆柊鏄犲皠鐐篎IFO淇¤櫉(h脿o)

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鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
绗﹀悎REACH妯�(bi膩o)婧�(zh菙n)	鏄�
鐙€鎱�(t脿i)	娲绘€�
鏅�(sh铆)閻橀牷鐜�-鏈€澶у€�	1205.0 MHz
JESD-30浠ｇ⒓	S-PBGA-B1148
JESD-609浠ｇ⒓	E0
绺絉AM浣嶆暩(sh霉)	2949120
CLB鏁�(sh霉)閲�	6656.0
杓稿叆鏁�(sh霉)閲�	640.0
閭忚集鍠厓鐨勬暩(sh霉)閲�	59904.0
杓稿嚭鏁�(sh霉)閲�	640.0
绲傜鏁�(sh霉)閲�	1148
绲勭箶	6656 CLBS
宄板€煎洖娴佹韩搴�(鈩�)	225
璩囨牸鐙€鎱�(t脿i)	涓嶅悎鏍�
鍧愬Э楂樺害-鏈€澶�	3.4姣背
瀛愰鍒�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
闆绘簮闆诲	1.2 V
闆绘簮闆诲-鏈€灏忓€�	1.14 V
闆绘簮闆诲-鏈€澶у€�	1.26 V
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
绲傜瀹屾垚	閷�/閴�(Sn63Pb37)
绲傜琛ㄦ牸	鐞�
绲傜闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅�(sh铆)闁揁宄板€煎洖娴佹韩搴�-鏈€澶у€�(s)	涓夊崄
闀峰害	35.0姣背
瀵害	35.0姣背
鍖呰楂旀潗鏂�	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰９浠ｇ⒓	BGA
鍖呯瓑鍍�(ji脿)浠ｇ⒓	BGA1148,34X34,40
鍖呰褰㈢媭	寤ｅ牬
鍖呰棰�(f膿ng)鏍�	缍�(w菐ng)鏍奸櫍鍒�
鍒堕€犲晢鍖呰瑾槑	FBGA-1148