XC4VSX25-11FFG668I 鏅傞枔锛�2022/10/24 16:45:42 闁辫畝锛�691

鐢�(ch菐n)鍝佸瀷铏� XC4VSX25-11FFG668I鎻忚堪IC FPGA 320 I/O 668FCBGA鍒嗛闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)

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Virtex-4 SX锛氱敤浜庢暩(sh霉)瀛椾俊铏熻檿鐞�(DSP)鎳�(y墨ng)鐢ㄧ殑楂樻€ц兘瑙ｆ焙鏂规

Xesium鏅傞悩鎶€琛�(sh霉)

鏁�(sh霉)瀛楁檪閻樼鐞嗗櫒(DCM)濉�

闄勫姞鐨勭浉浣嶅尮閰嶆檪閻樺垎闋诲櫒(PMCD)

宸垎鍏ㄧ悆鏅傞悩

XtremeDSP鍒囩墖

18 x 18锛屼簩閫插埗瑁滅⒓锛屽付绗﹁櫉涔樻暩(sh霉)

鍙伕鐨勭閬撻殠娈�

鍏�(n猫i)缃疮鍔犲櫒(48浣�)鍜屽姞娉曞櫒/娓涙硶鍣�

鏅鸿兘RAM鍏�(n猫i)瀛樺堡娆＄祼(ji茅)妲�(g貌u)

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1.5V鑷�3.3VI / O鎿嶄綔

鍏�(n猫i)缃瓹hipSync婧愬悓姝ユ妧琛�(sh霉)

鏁�(sh霉)瀛楁帶鍒堕樆鎶�(DCI)鏈夋簮绲傜

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鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
绗﹀悎REACH妯�(bi膩o)婧�(zh菙n)	鏄�
绗﹀悎姝愮洘RoHS妯�(bi膩o)婧�(zh菙n)	鏄�
鐙€鎱�(t脿i)	娲绘€�
鏅傞悩闋荤巼-鏈€澶у€�	1205.0 MHz
JESD-30浠ｇ⒓	S-PBGA-B668
JESD-609浠ｇ⒓	E1
绺絉AM浣嶆暩(sh霉)	2359296
CLB鏁�(sh霉)閲�	2560.0
杓稿叆鏁�(sh霉)閲�	320.0
閭忚集鍠厓鐨勬暩(sh霉)閲�	23040.0
杓稿嚭鏁�(sh霉)閲�	320.0
绲傜鏁�(sh霉)閲�	668
绲勭箶	2560 CLBS
宄板€煎洖娴佹韩搴�(鈩�)	245
璩囨牸鐙€鎱�(t脿i)	涓嶅悎鏍�
鍧愬Э楂樺害-鏈€澶�	2.85姣背
瀛愰鍒�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
闆绘簮闆诲	1.2 V
闆绘簮闆诲-鏈€灏忓€�	1.14 V
闆绘簮闆诲-鏈€澶у€�	1.26 V
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
绲傜瀹屾垚	閷�/閵€/閵�(Sn95.5Ag4.0Cu0.5)
绲傜琛ㄦ牸	鐞�
绲傜闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅傞枔@宄板€煎洖娴佹韩搴�-鏈€澶у€�	涓夊崄
闀峰害	27.0姣背
瀵害	27.0姣背
鍖呰楂旀潗鏂�	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰９浠ｇ⒓	BGA
鍖呯瓑鍍逛唬纰�	BGA668,26X26,40
鍖呰褰㈢媭	寤ｅ牬
鍖呰棰�(f膿ng)鏍�	缍�(w菐ng)鏍奸櫍鍒�
鍒堕€犲晢鍖呰瑾槑	鐒￠墰锛孎(xi脿n)BGA-668