鏅傞枔锛�2022/10/24 13:46:28
闁辫畝锛�679
鐢�(ch菐n)鍝佸瀷铏� | XC5VFX100T-1FFG1136C |
鎻忚堪 | IC FPGA 640杓稿叆/杓稿嚭1136FCBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鐢�(ch菐n)鍝佸瀷铏� | XC5VFX100T-1FFG1136C |
鎻忚堪 | IC FPGA 640杓稿叆/杓稿嚭1136FCBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鍒堕�犲晢 | Xilinx鍏徃 |
绯诲垪 | Virtex?-5FXT |
鎵撳寘 | 鎵樼洡 |
闆朵欢鐙�鎱�(t脿i) | 娲绘�� |
闆诲-闆绘簮 | 0.95V1.05V |
宸ヤ綔婧害 | 0掳C85掳C(TJ) |
鍖呰/绠� | 1136-BBGA锛孎(xi脿n)CBGA |
渚涙噳鍟嗚ō鍌欏寘瑁� | 1136-FCBGA(35x35) |
鍩烘湰闆朵欢铏� | XC5VFX100T |
Virtex-5FXT锛氬叿鏈夐珮绱氫覆琛岄�ｆ帴鐨勯珮鎬ц兘宓屽叆寮忕郴绲�(t菕ng)
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鐪熸鐨�6杓稿叆鏌ユ壘琛�(LUT)鎶�琛�
闆�5-LUT閬搁爡
鏀归�茬殑娓涘皯韬嶉粸璺敱
64浣嶅垎甯冨紡RAM閬搁爡
SRL32/DualSRL16閬搁爡
寮峰ぇ鐨勬檪閻樼鐞嗙璨�(CMT)鏅傞悩
鏁�(sh霉)瀛楁檪閻樼鐞嗗櫒(DCM)妯″鐢ㄤ簬闆跺欢閬茬珐娌�锛岄牷鐜囧悎鎴愬拰鏅傞悩鐩哥Щ
PLL妯″锛岀敤浜庤几鍏ユ姈鍕曟烤娉�锛岄浂寤堕伈绶╂矕锛岄牷鐜囧悎鎴愬拰鐩镐綅鍖归厤鏅傞悩鍒嗛牷
36Kb濉奟AM/FIFO
鐪熸鐨勯洐绔彛RAM濉�
澧炲挤鐨勫彲閬稿彲绶ㄧ▼FIFO閭忚集
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(鍙伕)灏囨瘡鍊嬪绶ㄧ▼鐐哄叐鍊嬬崹绔嬬殑18-Kbit濉�
楂樻�ц兘骞惰SelectIO鎶�琛�
1.2鑷�3.3VI/O鎿嶄綔
浣跨敤ChipSync?鎶�琛撶殑婧愬悓姝ユ帴鍙�
鏁�(sh霉)鎺ч樆鎶�(DCI)鏈夋簮绲傜
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楂橀�熷瓨鍎插櫒鎺ュ彛鏀寔
鍏堥�茬殑DSP48ESlice
25x18锛屼簩閫插埗瑁滅⒓锛屼箻娉�
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SPI鍜屽苟琛孎LASH鎺ュ彛
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涓夋ā10/100/1000Mb/s浠ュお缍�(w菐ng)MAC
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TXT鍜孎XT骞宠嚭
PowerPC440寰檿鐞嗗櫒
鍍匜XT骞宠嚭
RISC鏋舵
7绱氭祦姘寸窔
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鍎�(y艒u)鍖栫殑铏曠悊鍣ㄦ帴鍙ｇ祼妲�(绺辨┇鍒�)
65绱嶇背閵匔MOS宸ヨ棟鎶�琛�
1.0V鏍稿績闆诲
楂樹俊铏熷畬鏁存�у�掕鑺墖灏佽锛屾彁渚涙婧栨垨鐒￠墰灏佽閬搁爡
鍒堕�犲晢鍖呰瑾槑 | 35 X 35 MM锛岀劇閴�锛孎(xi脿n)BGA-1136 |
绗﹀悎姝愮洘RoHS | 鏄� |
鐙�鎱�(t脿i) | 娲绘�� |
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
鏈�澶ф檪閻橀牷鐜� | 1098.0鍏嗚但 |
JESD-30浠ｇ⒓ | S-PBGA-B1136 |
JESD-609浠ｇ⒓ | e1 |
绺絉AM浣� | 8404992 |
CLB鏁�(sh霉)閲� | 8960.0 |
杓稿叆鏁�(sh霉)閲� | 640.0 |
閭忚集鍠厓鏁�(sh霉) | 102400.0 |
杓稿嚭鏁�(sh霉)閲� | 640.0 |
绔瓙鏁�(sh霉) | 1136 |
绲勭箶 | 8960 CLBS |
鍖呰涓婚珨鏉愭枡 | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰浠ｇ⒓ | BGA |
鍖呰绛夋晥浠ｇ⒓ | BGA1136,34X34,40 |
鍖呰褰㈢媭 | 鍥涙柟褰� |
鍖呰褰㈠紡 | 缍�(w菐ng)鏍奸櫍鍒� |
宄板�煎洖娴佹韩搴�(鈩�) | 245 |
闆绘簮 | 1,2.5 |
搴ч珮 | 3.4姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲妯欑ū | 1.0浼� |
鏈�灏忎緵闆婚浕澹� | 0.95浼� |
鏈�澶ч浕婧愰浕澹� | 1.05浼� |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛� | CMOS |
绲傜瀹屾垚 | 閷�/閵�/閵�(Sn95.5Ag4.0Cu0.5) |
绲傜琛ㄦ牸 | 鐞� |
绔瓙闁撹窛 | 1.0姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅傞枔@宄板�煎洖娴佹韩搴�-鏈�澶�(绉�) | 30 |
闀峰害 | 35.0姣背 |
瀵害 | 35.0姣背 |
