鏅傞枔锛�2025/4/30 15:44:27
闁辫畝锛�36
XC5VLX110-1FF1760C 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-5 绯诲垪 FPGA 鑺墖涓殑涓�鍊嬪瀷铏�銆俈irtex-5 绯诲垪 FPGA 鍩轰簬鍏堥�茬殑 65nm 宸ヨ棟鎶�琛撳埗閫�锛屽叿鏈夐珮鎬ц兘銆侀珮瀵嗗害鍜屼綆鍔熻�楃殑鐗归粸銆俋C5VLX110-1FF1760C 鎻愪緵璞愬瘜鐨勯倧杓硣婧�銆佸祵鍏ュ紡瀛樺劜鍣ㄦā濉�銆丏SP 妯″浠ュ強楂橀�熶覆琛屾敹鐧�(f膩)鍣�锛岄仼鐢ㄤ簬閫氫俊銆佷俊铏熻檿鐞�銆佸湒鍍忚檿鐞嗙瓑澶氱ó寰╅洔鎳夌敤闋樺煙銆�
銆�銆�瑭茶姱鐗囬倓鏀寔澶氱ó閰嶇疆閬搁爡锛屽寘鎷緸闁冨瓨鍟熷嫊鎴栭�氶亷 JTAG 鎺ュ彛閫茶绶ㄧ▼锛屾彁渚涗簡楂樺害鐨勯潏娲绘�у拰鍙潬鎬с��
绯诲垪锛歏irtex-5
銆�銆�鍨嬭櫉锛歑C5VLX110-1FF1760C
銆�銆�宸ヨ棟锛�65nm
銆�銆�FPGA 鏋舵锛歀UT-based
銆�銆�閭忚集鍠厓鏁搁噺锛氱磩 110,000 鍊�
銆�銆�Block RAM锛�3,990 Kb
銆�銆�DSP48 Slice 鏁搁噺锛�220
銆�銆�I/O 寮曡叧鏁搁噺锛氭渶澶� 1,040 鍊�
銆�銆�涓茶鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂� 11.18 Gbps
銆�銆�宸ヤ綔婧害鑼冨湇锛氬晢妤�(y猫)绱氾紙0掳C 鑷� 85掳C锛�
銆�銆�灏佽椤炲瀷锛欶FG1760 (1760-Pin Fine Pitch BGA)
XC5VLX110-1FF1760C 鎻愪緵浜嗗崜瓒婄殑鎬ц兘鍜岄泦鎴愬害锛屾槸 Virtex-5 绯诲垪涓純鐐洪珮绔殑鍨嬭櫉涔嬩竴銆傚叾涓昏鐗规�у寘鎷細
銆�銆�1. 楂樺閲忛倧杓硣婧�锛岃兘澶犲鐝惧京闆滅殑鏁稿瓧闆昏矾瑷▓銆�
銆�銆�2. 鍏х疆澶у閲� Block RAM锛屾敮鎸佹暩鎿氱珐娌栧拰瀛樺劜鍔熻兘銆�
銆�銆�3. DSP48 Slice 鐨勫姞鍏ヤ娇鍏跺湪鏁稿瓧淇¤櫉铏曠悊浠诲嫏涓〃鐝惧劒(y艒u)鐣�锛屼緥濡傛烤娉�銆丗FT 鍜岀煩闄ｉ亱绠楃瓑銆�
銆�銆�4. 鏀寔楂橀仈 11.18 Gbps 鐨勯珮閫熶覆琛屾敹鐧�(f膩)鍣紝閬╁悎闇�瑕侀珮甯跺鏁告摎鍌宠几鐨勬噳鐢ㄥ牬鏅�銆�
銆�銆�5. 鎻愪緵闈堟椿鐨� I/O 妯欐簴鏀寔锛屽寘鎷� LVCMOS銆丩VDS 绛夊绋父瑕嬫帴鍙ｅ崝(xi茅)璀�銆�
銆�銆�6. 鍏峰倷鍕曟厠(t脿i)鍔熻�楃鐞嗗姛鑳斤紝鍙劒(y艒u)鍖栫郴绲�(t菕ng)鍔熻��銆�
銆�銆�7. 閰嶅悎 Xilinx 鐨勯枊鐧�(f膩)宸ュ叿锛堝 ISE 鎴� Vivado锛�锛屽彲浠ュ揩閫熷畬鎴愯ō瑷堣几鍏�銆佺稖鍚�銆佸竷灞�甯冪窔鍙婇璀夈��
XC5VLX110-1FF1760C 鍥犲叾楂樻�ц兘鍜岄珮闆嗘垚搴�锛屽唬娉涙噳鐢ㄤ簬浠ヤ笅闋樺煙锛�
銆�銆�1. 閫氫俊瑷倷锛氬鐒＄窔鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙涓殑鏁告摎鍖呰檿鐞嗚垏杞夌櫦(f膩)銆�
銆�銆�2. 鍦栧儚鑸囪闋昏檿鐞嗭細瀵︽檪鍦栧儚澧炲挤銆佽闋荤法纰艰В纰肩瓑鍔熻兘銆�
銆�銆�3. 鏁告摎涓績鍔犻�燂細鐢ㄤ簬鍔犲瘑瑙ｅ瘑銆佸绺В澹撶府绛変换鍕�銆�
銆�銆�4. 娓│娓噺鍎�鍣細淇¤櫉鐧�(f膩)鐢熷櫒銆佺ず娉㈠櫒绛夎ō鍌欑殑鏍稿績鎺у埗鍠厓銆�
銆�銆�5. 閱�(y墨)鐧傛垚鍍忥細瓒呰伈娉㈡垚鍍忋�丆T 鎺冩弿绛夐啱(y墨)鐧傝ō鍌欑殑鏁告摎閲囬泦鑸囪檿鐞�銆�
銆�銆�6. 宸ユキ(y猫)鑷嫊鍖栵細姗熷櫒浜烘帶鍒�銆侀亱鍕曟帶鍒剁瓑寰╅洔瀵︽檪鎺у埗浠诲嫏銆�
銆�銆�7. 鑸┖鑸ぉ鑸囧湅闃诧細闆烽仈淇¤櫉铏曠悊銆佽(w猫i)鏄熼�氫俊绛夊皪鍙潬鎬у拰鎬ц兘瑕佹眰妤甸珮鐨勫牬鍚�銆�
XC5VLX110T-1FF1760C
