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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XC5VLX110-1FFG1760C

XC5VLX110-1FFG1760C 鐧�(f膩)甯冩檪闁� 鏅傞枔锛�2025/5/28 20:30:44 鏌ョ湅 闁辫畝锛�8

XC5VLX110-1FFG1760C 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-5 绯诲垪 FPGA 鑺墖涓殑涓�鍊嬪瀷铏�銆傝┎绯诲垪鑺墖涓昏闈㈠悜楂樻�ц兘瑷堢畻銆佹暩(sh霉)瀛椾俊铏熻檿鐞嗗拰閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂界瓑鎳�(y墨ng)鐢ㄩ牁(l菒ng)鍩�锛屽叿鏈夐珮閭忚集瀵嗗害銆佽睈瀵岀殑 DSP Slice 鍜� Block RAM 璩囨簮銆傛鍨嬭櫉閲囩敤 65nm 鍒剁▼宸ヨ棟鍒堕�狅紝鎻愪緵楂橀仈 110K 鍊嬮倧杓柈鍏�锛屽苟鏀寔澶氱ó楂橀�熶覆琛屾帴鍙ｅ拰纭牳 IP 妯″锛岄仼鐢ㄤ簬寰�(f霉)闆滅殑瑷�(sh猫)瑷堥渶姹�銆�
銆�銆�瑭插櫒浠跺皝瑁濈偤 FFG1760锛屽付鏈夊ぇ閲� I/O 寮曡叧锛岄仼鍚堥渶瑕侀珮寮曡叧鏁�(sh霉)鐨勬噳(y墨ng)鐢ㄥ牬鏅紝鍚屾檪鍏峰倷闈堟椿鐨勬檪閻樼鐞嗗姛鑳藉拰浣庡姛鑰楁ā寮�銆�

鍙冩暩(sh霉)

鍨嬭櫉锛歑C5VLX110-1FFG1760C
銆�銆�绯诲垪锛歏irtex-5
銆�銆�鍒剁▼宸ヨ棟锛�65nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細110,400
銆�銆�DSP Slice 鏁�(sh霉)閲忥細360
銆�銆�Block RAM 瀹归噺锛�2,780 KB
銆�銆�閰嶇疆瀛樺劜椤炲瀷锛歋erial Flash PROM
銆�銆�I/O 閵�琛屾暩(sh霉)閲忥細54
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�鏍稿績闆诲锛�1.0V
銆�銆�I/O 闆诲锛�1.8V/2.5V/3.3V
銆�銆�灏佽褰㈠紡锛欶FG1760

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XC5VLX110-1FFG1760C 鎻愪緵浜嗗挤澶х殑閭忚集璩囨簮鍜岄珮搴﹀彲鎿村睍鎬х郴绲�(t菕ng)瑷�(sh猫)瑷�銆�
銆�銆�1. 楂樻�ц兘鏋舵(g貌u)锛氶噰鐢� Virtex-5 鐨勭当(t菕ng)涓� FPGA 鏋舵(g貌u)锛屽劒(y艒u)鍖栦簡鏅傚簭鏀舵杺鍜屾�ц兘琛ㄧ従(xi脿n)銆�
銆�銆�2. 鍏�(n猫i)缃‖鏍告ā濉婏細鍖呭惈 PowerPC 440 铏曠悊鍣�銆丳CI Express銆佸崈鍏嗕互澶恫(w菐ng)鍜� RocketIO 绛夌‖鏍� IP 妯″锛岃兘澶犻’钁楅檷浣庤ō(sh猫)瑷堝京(f霉)闆滃害銆�
銆�銆�3. 楂橀�熶覆琛岄�ｆ帴鑳藉姏锛氭敮鎸侀珮閬� 6.5Gbps 鐨勪覆琛屾暩(sh霉)鎿�(j霉)閫熺巼锛岄仼鐢ㄤ簬鍏夌簴閫氫俊鍜屽叾浠栭珮閫熸噳(y墨ng)鐢�銆�
銆�銆�4. 闈堟椿鐨勯浕婧愮鐞嗭細鏀寔鍕曟厠(t脿i)鍔熻�楄(di脿o)绡�(ji茅)鎶�琛�(sh霉)锛屽厑瑷卞湪閬嬭鏅傝(di脿o)鏁撮浕澹撲互瀵︾従(xi脿n)绡�(ji茅)鑳�銆�
銆�銆�5. 寤ｆ硾鐨勯枊鐧�(f膩)宸ュ叿鏀寔锛氫娇鐢� Xilinx ISE Design Suite 鎴� Vivado 宸ュ叿閺堥�茶瑷�(sh猫)瑷堥枊鐧�(f膩)锛屾彁渚涘緸 RTL 绶ㄧ⒓鍒版瘮鐗规祦鐢熸垚鐨勫畬鏁存祦绋嬫敮鎸併��
銆�銆�6. 澶氭ǎ鍖栫殑 I/O 鏀寔锛氬吋瀹瑰绋婧栭浕骞冲崝(xi茅)璀�锛屽 LVCMOS銆丩VDS 鍜� SATA锛岄仼鎳�(y墨ng)涓嶅悓鎳�(y墨ng)鐢ㄥ牬鏅殑闇�姹傘��

鎳�(y墨ng)鐢�

XC5VLX110-1FFG1闋�(l菒ng)鍩燂細
銆�銆�1. 閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂斤細濡傚熀绔�銆佽矾鐢卞櫒鍜屼氦鎻涙涓殑淇¤櫉铏曠悊鍜屾暩(sh霉)鎿�(j霉)鍌宠几浠诲嫏(w霉)銆�
銆�銆�2. 鍦栧儚鑸囪闋昏檿鐞嗭細鐢ㄤ簬瀵︽檪鍦栧儚鍒嗘瀽銆佽闋荤法纰艰В纰煎拰鍦栧舰娓叉煋绛夋噳(y墨ng)鐢�銆�
銆�銆�3. 楂樻�ц兘瑷堢畻锛氫綔鐐哄崝(xi茅)铏曠悊鍣ㄥ姞閫熺煩闄ｉ亱绠楁垨鍔犲瘑绠楁硶绛夊京(f霉)闆滆▓绠�銆�
銆�銆�4. 閱�(y墨)鐧傝ō(sh猫)鍌欙細濡傝秴鑱叉尝鎴愬儚鍎�涓殑淇¤櫉閲囬泦鑸囪檿鐞�銆�
銆�銆�5. 娓│娓噺鍎�鍣細渚嬪绀烘尝鍣ㄣ�侀牷璀滃垎鏋愬剙涓殑鍓嶇鏁�(sh霉)鎿�(j霉)閲囬泦鍜屽悗绔暩(sh霉)鎿�(j霉)鍒嗘瀽銆�
銆�銆�6. 宸ユキ(y猫)鑷嫊鍖栨帶鍒讹細瀵︾従(xi脿n)寰�(f霉)闆滅殑閬嬪嫊鎺у埗鍜屽鏅傜洠(ji膩n)鎺у姛鑳�銆�

鏇夸唬鍨嬭櫉

XC5VLX110T-1FFG1760C
銆�銆�XC5VLX110-2FFG1760C
銆�銆�XC5VLX110T-2FFG1760C

xc5vlx110-1ffg1760c鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�
  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児

xc5vlx110-1ffg1760c鐢�(ch菐n)鍝�

xc5vlx110-1ffg1760c鍙冩暩(sh霉)

  • 妯欐簴鍖呰1
  • 椤炲垾闆嗘垚闆昏矾 (IC)
  • 瀹跺涵宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛�
  • 绯诲垪Virtex®-5 LX
  • LAB/CLB鏁�(sh霉)8640
  • 閭忚集鍏冧欢/鍠厓鏁�(sh霉)110592
  • RAM 浣嶇附瑷�4718592
  • 杓稿叆/杓稿嚭鏁�(sh霉)800
  • 闁�鏁�(sh霉)-
  • 闆绘簮闆诲0.95 V ~ 1.05 V
  • 瀹夎椤炲瀷琛ㄩ潰璨艰
  • 宸ヤ綔婧害0°C ~ 85°C
  • 灏佽/澶栨1760-BBGA锛孎(xi脿n)CBGA
  • 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�1760-FCBGA
  • 閰嶇敤568-5088-ND - BOARD DEMO DAC1408D750HW-V5-ML523-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1760-500-G-ND - BOARD DEV VIRTEX 5 FF1760