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XC5VLX110-3FFG1760C 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-5 绯诲垪 FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛夎姱鐗�銆傝┎绯诲垪鑺墖浠ュ叾楂樻�ц兘銆侀珮瀵嗗害閭忚集璩囨簮鍜岃睈瀵岀殑澶栬ō鎺ュ彛鑰岃憲绋憋紝寤ｆ硾鎳夌敤浜庨�氫俊銆佷俊铏熻檿鐞�銆佸湒鍍忚檿鐞嗙瓑闋樺煙銆�
銆�銆�Virtex-5 绯诲垪閲囩敤浜嗗厛閫茬殑 65nm 鍒堕�犲伐钘�锛屾彁渚涘挤澶х殑閭忚集鍔熻兘鍜岄珮閫熶覆琛岄�ｆ帴鑳藉姏銆俋C5VLX110 鏄叾涓竴娆句腑楂樼鍨嬭櫉锛屽叿鏈夎純楂樼殑閭忚集鍠厓鏁�(sh霉)閲忓拰濉婂瓨鍎插櫒瀹归噺锛岄仼鐢ㄤ簬寰╅洔绯荤当(t菕ng)瑷▓銆�
鍨嬭櫉锛歑C5VLX110-3FFG1760C
銆�銆�绯诲垪锛歏irtex-5
銆�銆�鍝佺墝锛歑ilinx
銆�銆�鍒剁▼宸ヨ棟锛�65nm
銆�銆�閫熷害绛夌礆锛�-3
銆�銆�I/O 鏁�(sh霉)閲忥細1084
銆�銆�閰嶇疆闁冨瓨锛氱劇鍏х疆
銆�銆�閭忚集鍠厓鏁�(sh霉)锛氱磩 110K
銆�銆�Block RAM 瀹归噺锛氱磩 6.2Mb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細480
銆�銆�灏佽椤炲瀷锛欶FG1760
銆�銆�宸ヤ綔婧害鑼冨湇锛氬晢妤�(y猫)绱� (0掳C 鑷� 85掳C)
XC5VLX110-3FFG1760C 鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樻�ц兘閭忚集绲愭锛屾敮鎸佸京闆滅殑鏁�(sh霉)瀛椾俊铏熻檿鐞嗕换鍕欍��
銆�銆�2. 闆嗘垚鐨� RocketIO 鏀剁櫦(f膩)鍣ㄨ兘澶犳彁渚涢珮閬� 6.5Gbps 鐨勪覆琛屾暩(sh霉)鎿�(j霉)鍌宠几閫熺巼銆�
銆�銆�3. 鎻愪緵澶ч噺 DSP Slice 妯″锛岄仼鍚堥珮鏁堝鐝�(xi脿n)涔樻硶绱姞绛夐亱绠�銆�
銆�銆�4. 鍏х疆澶у閲� Block RAM 鍜屽垎甯冨紡 RAM 璩囨簮锛屾豢瓒冲悇绋瓨鍎查渶姹傘��
銆�銆�5. 鏀寔澶氱ó鏅傞悩绠＄悊鍔熻兘锛屼緥濡� PLL 鍜� DCM锛岀敤浜庣簿纰烘帶鍒舵檪閻樹俊铏�銆�
銆�銆�6. 鎻愪緵闈堟椿鐨勭敤鎴� I/O 鎺ュ彛锛屾敮鎸佸绋婧栭浕骞冲崝(xi茅)璀�銆�
銆�銆�7. 鏀寔閮ㄥ垎閲嶉厤缃妧琛�锛屽厑瑷卞湪閬嬭鏅傚嫊鎱�(t脿i)淇敼瑷▓鐨勯儴鍒嗗崁(q奴)鍩�銆�
銆�銆�8. 鍙�氶亷 SPI銆両IC 鎴� BPI 鎺ュ彛閫茶澶栭儴閰嶇疆銆�
XC5VLX110-3FFG1760C 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 閫氫俊瑷倷锛屽鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙涓殑鏁�(sh霉)鎿�(j霉)鍖呰檿鐞嗘ā濉娿��
銆�銆�2. 鍦栧儚鍜岃闋昏檿鐞嗙郴绲�(t菕ng)锛屼緥濡傚鏅傚湒鍍忓绺�銆佽В纰煎拰婵炬尝銆�
銆�銆�3. 閱�(y墨)鐧傝ō鍌欎腑鐨勬暩(sh霉)鎿�(j霉)閲囬泦鑸囦俊铏熻檿鐞�銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栦腑鐨勯亱鍕曟帶鍒跺拰瀵︽檪鐩�(ji膩n)鎺�銆�
銆�銆�5. 楂樻�ц兘瑷堢畻骞宠嚭涓殑鍗�(xi茅)铏曠悊鍣ㄦā濉娿��
銆�銆�6. 娓│鑸囨脯閲忚ō鍌欎腑鐨勪俊铏熺敓鎴愯垏鍒嗘瀽鍔熻兘銆�
銆�銆�鍏跺挤澶х殑閭忚集璩囨簮鍜岄珮閫熸帴鍙ｄ娇鍏舵垚鐐洪渶瑕侀珮鎬ц兘瑷堢畻鍜屽京闆滄帶鍒舵噳鐢ㄧ殑鐞嗘兂閬告搰銆�
XC5VLX110T-3FFG1760C
銆�銆�XC5VLX110-2FFG1760C
銆�銆�XC5VLX110T-2FFG1760C
