鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫�(ch菐ng)缍�(w菐ng)
鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺(c猫)
鏅�(sh铆)闁擄細2022/10/20 13:43:02
闁辫畝锛�670
鐢�(ch菐n)鍝佸瀷铏�(h脿o) XC5VLX30-2FF324C鎻忚堪IC FPGA 220 I/O 324FCBGA鍒嗛闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪)
鐢�(ch菐n)鍝佸瀷铏�(h脿o) XC5VLX30-2FF324C鎻忚堪IC FPGA 220 I/O 324FCBGA鍒嗛闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪)鐢熺敘(ch菐n)寤犲Xilinx鍏徃绯诲垪Virtex?-5 LX閮ㄥ垎鐙�鎱�(t脿i)娲绘�ч浕澹�-闆绘簮0.95V~1.05V宸ヤ綔婧害0掳C~85掳C(TJ)鍖�/绠�324-BBGA锛孎(xi脿n)CBGA渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘324-FCBGA(19x19)鍩虹(ch菙)閮ㄤ欢铏�(h脿o)XC5VLX30
浜斿��(g猫)骞宠嚭(t谩i)LX锛孡XT锛孲XT锛孴XT鍜孎XT
Virtex-5 LX锛氶珮鎬ц兘閫氱敤閭忚集鎳�(y墨ng)鐢�
Virtex-5 LXT锛氬叿鏈夐珮绱�(j铆)涓茶閫ｆ帴鐨勯珮鎬ц兘閭忚集
Virtex-5 SXT锛氬叿鏈夐珮绱�(j铆)涓茶閫ｆ帴鐨勯珮鎬ц兘淇¤櫉(h脿o)铏曠悊鎳�(y墨ng)鐢�
Virtex-5 TXT锛氬叿鏈夐洐瀵嗗害楂樼礆(j铆)涓茶閫ｆ帴鐨勯珮鎬ц兘绯荤当(t菕ng)
Virtex-5 FXT锛氬叿鏈夐珮绱�(j铆)涓茶閫ｆ帴鐨勯珮鎬ц兘宓屽叆寮忕郴绲�(t菕ng)
璺ㄥ钩鑷�(t谩i)鍏煎鎬�
LXT锛孲XT鍜孎XT鍣ㄤ欢閲囩敤鍙(di脿o)闆诲瑾�(di脿o)绡�(ji茅)鍣�锛屽湪鍚屼竴灏佽涓吋瀹�
鏈�鍏堥��(j矛n)锛岄珮鎬ц兘锛屾渶浣冲埄鐢ㄧ巼鐨凢PGA鏋舵(g貌u)
鐪熸鐨�6杓稿叆鏌ユ壘琛�(LUT)鎶�琛�(sh霉)
闆�5-LUT閬搁爡(xi脿ng)
鏀归��(j矛n)鐨勬笡灏戣烦韬嶈矾鐢�
64浣嶅垎甯冨紡RAM閬搁爡(xi脿ng)
SRL32 / Dual SRL16閬搁爡(xi脿ng)
寮�(qi谩ng)澶х殑鏅�(sh铆)閻樼鐞嗙璨�(CMT)鏅�(sh铆)閻�
鏁�(sh霉)瀛楁檪(sh铆)閻樼鐞嗗櫒(DCM)闃绘闆跺欢閬茬珐娌�锛岄牷鐜囧悎鎴愬拰鏅�(sh铆)閻樼浉绉�
PLL妯″鐢ㄤ簬杓稿叆鎶栧嫊(d貌ng)婵炬尝锛岄浂寤堕伈绶╂矕锛岄牷鐜囧悎鎴愬拰鐩镐綅鍖归厤鏅�(sh铆)閻樺垎闋�
36-Kbit Block RAM / FIFO
鐪熸鐨勯洐绔彛RAM妯″
澧炲挤(qi谩ng)鐨勫彲閬稿彲绶ㄧ▼FIFO閭忚集
鍙法绋嬬殑
鐪熸鐨勯洐绔彛瀵害鍙仈(d谩)x36
绨�(ji菐n)鍠殑闆欑鍙ｅ搴﹀彲閬�(d谩)x72
鍏�(n猫i)缃彲閬哥殑绯鹃尟(cu貌)闆昏矾
鍙伕鎿囧皣姣忓��(g猫)濉婄法绋嬬偤鍏╁��(g猫)鐛�(d煤)绔嬬殑18-Kbit濉�
楂樻�ц兘骞惰SelectIO鎶�琛�(sh霉)
1.2鑷�3.3VI / O鎿嶄綔
浣跨敤ChipSync?鎶�琛�(sh霉)閫�(j矛n)琛屾簮鍚屾鎺ュ彛
鏁�(sh霉)瀛楁帶鍒堕樆鎶�(DCI)鏈夋簮绲傜
闈堟椿鐨勭窗(x矛)绮掑害I / O閵�琛屾キ(y猫)鍕�(w霉)
楂橀�熷収(n猫i)瀛樻帴鍙ｆ敮鎸�
鍏堥��(j矛n)鐨凞SP48E鍒囩墖
25 x 18锛屼簩閫�(j矛n)鍒惰(b菙)纰硷紝涔樻硶
鍙伕鐨勫姞娉曞櫒锛屾笡娉曞櫒鍜岀疮鍔犲櫒
鍙伕鐨勬祦姘寸窔
鍙伕鐨勬寜浣嶉倧杓姛鑳�
灏堢敤绱�(j铆)鑱�(li谩n)閫ｆ帴
闈堟椿鐨勯厤缃伕闋�(xi脿ng)
SPI鍜屽苟琛孎LASH鎺ュ彛
鍏锋湁灏堢敤鍥為��閲嶉厤缃倧杓殑澶氭瘮鐗规祦鏀寔
鑷嫊(d貌ng)绺界窔瀵害妾㈡脯(c猫)鍔熻兘
鎵�鏈夎ō(sh猫)鍌欎笂鐨勭郴绲�(t菕ng)鐩�(ji膩n)鎺у姛鑳�
鐗囦笂/鐗囧鐔辩洠(ji膩n)鎺�
鐗囦笂/鐗囧闆绘簮鐩�(ji膩n)鎺�
JTAG瑷晱鎵�鏈夊彈鐩�(ji膩n)鎺х殑鏁�(sh霉)閲�
鐢ㄤ簬PCI Express瑷�(sh猫)瑷�(j矛)鐨勯泦鎴愮榛�(di菐n)妯″
LXT锛孲XT锛孴XT鍜孎XT骞宠嚭(t谩i)
绗﹀悎PCI Express Base Specification 1.1
姣忓��(g猫)濉妜1锛寈4鎴杧8閫氶亾鏀寔
鑸嘡ocketIO?鏀剁櫦(f膩)鍣ㄩ厤鍚堜娇鐢�
涓夋ā10/100/1000 Mb / s浠ュお缍�(w菐ng)MAC
LXT锛孲XT锛孴XT鍜孎XT骞宠嚭(t谩i)
RocketIO鏀剁櫦(f膩)鍣ㄥ彲鐢ㄤ綔PHY鎴栦娇鐢ㄨū澶氳粺MII(濯掗珨鐛�(d煤)绔嬫帴鍙�)閬搁爡(xi脿ng)閫ｆ帴鍒板閮≒HY
RocketIO GTP鏀剁櫦(f膩)鍣�100 Mb / s鑷�3.75 Gb / s
LXT鍜孲XT骞宠嚭(t谩i)
RocketIO GTX鏀剁櫦(f膩)鍣ㄩ�熷害鐐�150 Mb / s鑷�6.5 Gb / s
TXT鍜孎XT骞宠嚭(t谩i)
PowerPC 440寰檿鐞嗗櫒
鍍呴檺FXT骞宠嚭(t谩i)
RISC鏋舵(g貌u)
7闅庢绠￠亾
鍖呮嫭32 KB鐨勬寚浠ゅ拰鏁�(sh霉)鎿�(j霉)绶╁瓨
鍎�(y艒u)鍖栫殑铏曠悊鍣ㄦ帴鍙ｇ祼(ji茅)妲�(g貌u)(crossbar)
65绱嶇背閵匔MOS宸ヨ棟鎶�琛�(sh霉)
1.0V鏍稿績闆诲
楂樹俊铏�(h脿o)瀹屾暣鎬у�掕鑺墖灏佽锛屾彁渚涙(bi膩o)婧�(zh菙n)鎴栫劇閴涘皝瑁濋伕闋�(xi脿ng)
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪 |
绗﹀悎REACH妯�(bi膩o)婧�(zh菙n) | 鏄� |
鐙�鎱�(t脿i) | 娲绘�� |
鏅�(sh铆)閻橀牷鐜�-鏈�澶у�� | 1265.0 MHz |
JESD-30浠ｇ⒓ | S-PBGA-B324 |
JESD-609浠ｇ⒓ | E0 |
绺絉AM浣嶆暩(sh霉) | 1179648 |
CLB鏁�(sh霉)閲� | 2400.0 |
杓稿叆鏁�(sh霉)閲� | 220.0 |
閭忚集鍠厓鐨勬暩(sh霉)閲� | 30720.0 |
杓稿嚭鏁�(sh霉)閲� | 220.0 |
绲傜鏁�(sh霉)閲� | 324 |
宸ヤ綔婧害-鏈�灏忓�� | 0鈩� |
宸ヤ綔婧害-鏈�楂� | 85鈩� |
绲勭箶 | 2400 CLBS |
宄板�煎洖娴佹韩搴�(鈩�) | 225 |
闆绘簮 | 1,2.5 |
璩囨牸鐙�鎱�(t脿i) | 涓嶅悎鏍� |
鍧愬Э楂樺害-鏈�澶� | 2.85姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪 |
闆绘簮闆诲 | 1.0 V |
闆绘簮闆诲-鏈�灏忓�� | 0.95 V |
闆绘簮闆诲-鏈�澶у�� | 1.05 V |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛�(sh霉) | CMOS |
婧害绛夌礆(j铆) | 鍏朵粬 |
绲傜瀹屾垚 | 閷�/閴�(Sn63Pb37) |
绲傜琛ㄦ牸 | 鐞� |
绲傜闁撹窛 | 1.0姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅�(sh铆)闁揁宄板�煎洖娴佹韩搴�-鏈�澶у�� | 涓夊崄 |
闀�(zh菐ng)搴� | 19.0姣背 |
瀵害 | 19.0姣背 |
鍖呰楂旀潗鏂� | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰９浠ｇ⒓ | BGA |
鍖呯瓑鍍�(ji脿)浠ｇ⒓ | BGA324,18X18,40 |
鍖呰褰㈢媭 | 寤ｅ牬(ch菐ng) |
鍖呰棰�(f膿ng)鏍� | 缍�(w菐ng)鏍奸櫍鍒� |
鍒堕�犲晢鍖呰瑾槑 | 19 X 19 MM锛孎(xi脿n)BGA-324 |
IC鍨嬭櫉(h脿o)绱㈠紩锛� A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 0 1 2 3 4 5 6 7 8 9
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