鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng)
鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺
鏅傞枔锛�2022/10/20 10:20:18
闁辫畝锛�1146
鐢�(ch菐n)鍝佸瀷铏� | XC5VLX30T-1FFG323I |
鎻忚堪 | 闆嗘垚闆昏矾FPGA 172 I / O 323FCBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鍒堕�犲晢 | Xilinx鍏徃 |
绯诲垪 | Virtex?-5LXT |
鎵撳寘 | 鎵樼洡 |
闆朵欢鐙�鎱�(t脿i) | 娲绘�� |
闆诲-闆绘簮 | 0.95V?1.05V |
宸ヤ綔婧害 | -40掳C?100掳C(TJ) |
鍖呰/绠� | 323-BBGA锛孎(xi脿n)CBGA |
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁� | 323-FCBGA(19x19) |
鍩烘湰闆朵欢铏� | XC5VLX30 |
鐢�(ch菐n)鍝佸瀷铏� | XC5VLX30T-1FFG323I |
鎻忚堪 | 闆嗘垚闆昏矾FPGA 172 I / O 323FCBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鍒堕�犲晢 | Xilinx鍏徃 |
绯诲垪 | Virtex?-5LXT |
鎵撳寘 | 鎵樼洡 |
闆朵欢鐙�鎱�(t脿i) | 娲绘�� |
闆诲-闆绘簮 | 0.95V?1.05V |
宸ヤ綔婧害 | -40掳C?100掳C(TJ) |
鍖呰/绠� | 323-BBGA锛孎(xi脿n)CBGA |
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁� | 323-FCBGA(19x19) |
鍩烘湰闆朵欢铏� | XC5VLX30 |
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鈼忎笁妯�10/100/1000Mb/s浠ュお缍�(w菐ng)MAC
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鈼廟ocketIO GTX鏀剁櫦(f膩)鍣�150Mb/s鑷�6.5Gb/s
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銆俁ISC鏋舵(g貌u)
銆�7绱氭祦姘寸窔
銆傚寘鎷�32KB鐨勬寚浠ゅ拰鏁�(sh霉)鎿�(j霉)绶╁瓨
銆傚劒(y艒u)鍖栫殑铏曠悊鍣ㄦ帴鍙ｇ祼(ji茅)妲�(g貌u)(浜ゅ弶闁嬮棞(gu膩n))
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鈼�1.0V鏍稿績闆诲
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鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
鍒堕�犲晢鍖呰瑾槑 | 19 X 19 MM锛岀劇閴�锛孎(xi脿n)BGA-323 |
绗﹀悎姝愮洘RoHS | 鏄� |
鐙�鎱�(t脿i) | 娲绘�� |
鏈�澶ф檪閻橀牷鐜� | 1098.0鍏嗚但 |
JESD-30浠ｇ⒓ | S-PBGA-B323 |
JESD-609浠ｇ⒓ | e1 |
绺絉AM浣� | 1327104 |
CLB鏁�(sh霉)閲� | 2400.0 |
杓稿叆鏁�(sh霉)閲� | 172.0 |
閭忚集鍠厓鏁�(sh霉) | 30720.0 |
杓稿嚭鏁�(sh霉)閲� | 172.0 |
绔瓙鏁�(sh霉) | 323 |
绲勭箶 | 2400 CLBS |
鍖呰涓婚珨鏉愭枡 | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰浠ｇ⒓ | BGA |
鍖呰绛夋晥浠ｇ⒓ | BGA323,18X18,40 |
鍖呰褰㈢媭 | 鍥涙柟褰� |
鍖呰褰㈠紡 | 缍�(w菐ng)鏍奸櫍鍒� |
宄板�煎洖娴佹韩搴�(鈩�) | 250 |
闆绘簮 | 1,2.5 |
搴ч珮 | 2.85姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲妯�(bi膩o)绋� | 1.0浼� |
鏈�灏忎緵闆婚浕澹� | 0.95浼� |
鏈�澶ч浕婧愰浕澹� | 1.05浼� |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛�(sh霉) | CMOS |
绲傜瀹屾垚 | 閷�/閵�/閵�(Sn95.5Ag4.0Cu0.5) |
绲傜琛ㄦ牸 | 鐞� |
绔瓙闁撹窛 | 1.0姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅傞枔@宄板�煎洖娴佹韩搴�-鏈�澶�(绉�) | 30 |
闀峰害 | 19.0姣背 |
瀵害 | 19.0姣背 |
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