鏅傞枔锛�2025/5/10 9:31:10
闁辫畝锛�26
XC5VLX30T-2FFG323C 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-5 绯诲垪 FPGA 鑺墖涓殑涓�鍊嬪瀷铏熴�傝┎绯诲垪鑺墖鍩轰簬 65nm 宸ヨ棟鍒堕��锛屽叿鏈夐珮鎬ц兘銆侀珮閭忚集瀵嗗害鍜岃睈瀵岀殑澶栬ō鎺ュ彛绛夌壒榛�銆俋C5VLX30T 鎻愪緵浜嗗閬� 30K 鐨勯倧杓柈鍏冿紙Logic Cells锛�锛屽苟鏀寔澶氱ó宓屽叆寮� DSP 妯″銆丅lock RAM 鍜屽垎甯冨紡 RAM 璩囨簮锛岄仼鍚堢敤浜庨�氫俊銆佷俊铏熻檿鐞�銆佸湒鍍忚檿鐞嗗拰宸ユキ(y猫)鎺у埗绛夋噳鐢ㄩ牁鍩�銆�
銆�銆�瑭插瀷铏熶腑鐨勫叿楂斿弮鏁�(sh霉)鍚京濡備笅锛歑C 琛ㄧず Xilinx 鍏徃锛�5 琛ㄧず绗簲浠� Virtex 绯诲垪锛孷LX 琛ㄧず LX 鍨嬭櫉涓嬬殑澧炲挤鐗�锛�30 琛ㄧず绱� 30K 鐨勯倧杓柈鍏冭(gu墨)妯�锛孴 琛ㄧず鍟嗘キ(y猫)婧害鑼冨湇锛�2 琛ㄧず閫熷害绛夌礆锛孎(xi脿n)FG323 琛ㄧず灏佽椤炲瀷鐐� FGG323锛�323 寮曡叧锛�锛孋 琛ㄧず鍟嗙敤绱氬伐浣滅挵(hu谩n)澧�銆�
閭忚集鍠厓鏁�(sh霉)閲忥細30K
銆�銆�宸ヨ棟绡�(ji茅)榛烇細65nm
銆�銆�I/O 鏁�(sh霉)閲忥細284
銆�銆�Block RAM 瀹归噺锛�1.7Mb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細192
銆�銆�閰嶇疆妯″紡锛歋electMAP銆丮aster/Slave SPI銆丅oundary Scan
銆�銆�宸ヤ綔闆诲锛�1.0V 鏍搁浕澹�锛�1.8V I/O 闆诲
銆�銆�灏佽褰㈠紡锛欶FG323
銆�銆�閫熷害绛夌礆锛�-2
銆�銆�宸ヤ綔婧害鑼冨湇锛�0掳C 鑷� 85掳C
1. 楂樻�ц兘鏋舵锛歑C5VLX30T 閲囩敤 Virtex-5 绯诲垪鐨勭当(t菕ng)涓�鏋舵锛屾敮鎸侀珮閬� 500MHz 鐨勭郴绲�(t菕ng)鏅傞悩闋荤巼锛岄仼鐢ㄤ簬楂橀�熶俊铏熻檿鐞�銆�
銆�銆�2. 璞愬瘜鐨� DSP 鍔熻兘锛氬収缃� 192 鍊嬮珮鎬ц兘鐨� DSP Slice锛屾瘡鍊� Slice 鍖呭惈涔樻硶鍣ㄥ拰绱姞鍣�锛岄潪甯搁仼鍚堟暩(sh霉)瀛楁烤娉㈠櫒銆丗FT 鍜屽叾浠栨暩(sh霉)瀛搁亱绠椼��
銆�銆�3. 澶у閲� Block RAM锛氭彁渚� 1.7Mb 鐨� Block RAM 璩囨簮锛屽彲鐢ㄤ簬瀵︾従(xi脿n) FIFO銆佺珐瀛樺拰鏌ユ壘琛ㄧ瓑鍔熻兘銆�
銆�銆�4. 楂橀�熶覆琛屾敹鐧�(f膩)鍣細鏀寔闆嗘垚鐨� RocketIO 鏀剁櫦(f膩)鍣ㄦā濉�锛屽彲瀵︾従(xi脿n)楂橀仈 6.5Gbps 鐨勯珮閫熶覆琛岄�氫俊銆�
銆�銆�5. 鍙摯灞曟�э細閫氶亷纭牳 PCIe 鎺ュ彛鏀寔 PCI Express Gen1 鍜� Gen2 鍗�(xi茅)璀�锛屼究浜庤垏涓绘鎴栧叾浠栬ō鍌欓�ｆ帴銆�
銆�銆�6. 鍏х疆瑾胯│宸ュ叿锛氭敮鎸� ChipScope Pro 鍏ч儴閭忚集鍒嗘瀽鍔熻兘锛屼究浜庤ō瑷堥璀夊拰瑾胯│銆�
銆�銆�7. 浣庡姛鑰楀劒(y艒u)鍖栵細鍕曟厠(t脿i)鍔熻�楃鐞嗘妧琛撻’钁楅檷浣庨亱琛屽姛鑰�锛屾豢瓒充究鏀滃紡瑷倷鐨勯渶姹�銆�
XC5VLX30T-2FFG323C 寤ｆ硾鎳夌敤浜庡鍊嬮牁鍩�锛屽寘鎷絾涓嶉檺浜庯細
銆�銆�1. 閫氫俊绯荤当(t菕ng)锛氱敤浜庡熀甯朵俊铏熻檿鐞�銆佸崝(xi茅)璀拌綁鎻涘拰缍茬怠浜ゆ彌绛変换鍕�銆�
銆�銆�2. 瑕栭牷鑸囧湒鍍忚檿鐞嗭細鏀寔楂樻竻瑕栭牷绶ㄧ⒓瑙ｇ⒓銆佸湒鍍忓寮蜂互鍙婅▓绠楁瑕栬绠楁硶瀵︾従(xi脿n)銆�
銆�銆�3. 鏁�(sh霉)鎿�(j霉)涓績锛氫綔鐐哄崝(xi茅)铏曠悊鍣ㄦ垨鍔犻�熷櫒锛屾彁鍗囨湇鍕欏櫒鎬ц兘銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栵細鐢ㄤ簬閬嬪嫊鎺у埗銆佸鏅傛暩(sh霉)鎿�(j霉)閲囬泦鍜屽京闆滅畻娉曞鐝�(xi脿n)銆�
銆�銆�5. 閱�(y墨)鐧傛垚鍍忥細瀵︾従(xi脿n)瓒呰伈娉��丆T 鎺冩弿绛夐啱(y墨)鐧傝ō鍌欎腑鐨勬暩(sh霉)鎿�(j霉)铏曠悊鍔熻兘銆�
銆�銆�6. 娓│娓噺锛氱敤浣滀俊铏熺敓鎴愬櫒銆佺ず娉㈠櫒鍜屽崝(xi茅)璀板垎鏋愬剙鐨勬牳蹇冩帶鍒跺柈鍏�銆�
XC5VLX30T-3FFG323C
銆�銆�XC5VLX30T-2FF1136C
銆�銆�XC5VLX30T-3FF1136C
