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XC5VLX50T-3FF665C 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-5 绯诲垪 FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛夎姱鐗囦腑鐨勪竴鍊嬪瀷铏熴�俈irtex-5 绯诲垪鍩轰簬鍏堥�茬殑 65nm 宸ヨ棟鍒堕��锛屽叿鏈夐珮鎬ц兘銆侀珮閭忚集瀵嗗害鍜岃睈瀵岀殑宓屽叆寮忓姛鑳芥ā濉�銆�
銆�銆�瑭插瀷铏熸敮鎸� DSP Slice銆丅lock RAM 鍜屽垎甯冨紡 RAM 璩囨簮锛屽苟涓旈泦鎴愪簡澶氱ó纭牳 IP 妯″锛屼緥濡� PCIe銆丟igabit Ethernet 鍜� RocketIO 鏀剁櫦(f膩)鍣ㄧ瓑锛岄仼鍚堜簬閫氫俊銆佷俊铏熻檿鐞�銆佸湒鍍忚檿鐞嗗拰瑷堢畻瀵嗛泦鍨嬫噳鐢ㄩ牁鍩�銆�
绯诲垪锛歏irtex-5
銆�銆�鍨嬭櫉锛歑C5VLX50T-3FF665C
銆�銆�宸ヨ棟鍒剁▼锛�65nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 50,000 鍊�
銆�銆�閰嶇疆闁冨瓨锛氱劇鍏х疆闁冨瓨锛岄渶澶栫疆閰嶇疆瀛樺劜
銆�銆�鏈�澶у伐浣滈牷鐜囷細550 MHz
銆�銆�RAM 瀹归噺锛�1.5 Mb (Block RAM)
銆�銆�I/O 寮曡叧鏁�(sh霉)锛�665
銆�銆�渚涢浕闆诲锛氭牳蹇冮浕澹� 1.0V锛孖/O 闆诲 1.8V/2.5V/3.3V
銆�銆�灏佽椤炲瀷锛欶FG665 (Fine Pitch Flip Chip BGA)
銆�銆�閫熷害绛夌礆锛�-3 (鎬ц兘鍎�(y艒u)鍖栫礆)
XC5VLX50T-3FF665C 鎻愪緵浜嗗嚭鑹茬殑闈堟椿鎬у拰鎬ц兘锛岄仼鐢ㄤ簬寰╅洔鐨勬暩(sh霉)瀛楄ō瑷堜换鍕�銆�
銆�銆�1. 楂橀倧杓瘑搴︼細鎿佹湁绱� 50K 鐨勯倧杓柈鍏冿紝鑳藉瀵︾従(xi脿n)寰╅洔鐨勯倧杓姛鑳�銆�
銆�銆�2. 鍏у祵 DSP 鍔熻兘锛氶泦鎴愬閬� 240 鍊嬪皥鐢ㄧ殑 DSP Slice锛岄仼鍚堥�茶楂橀�熸暩(sh霉)瀛椾俊铏熻檿鐞嗐��
銆�銆�3. 澶у閲忓瓨鍎茶硣婧愶細鍖呭惈瓒呴亷 1.5Mb 鐨� Block RAM锛屽彲浣滅偤鏁�(sh霉)鎿�(j霉)绶╂矕鍗�(q奴)鎴栧皬鍨嬪瓨鍎插櫒浣跨敤銆�
銆�銆�4. 楂橀�熶覆琛屾帴鍙ｏ細RocketIO 鏀剁櫦(f膩)鍣ㄦ敮鎸侀珮閬� 6.5Gbps 鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼锛岄仼鍚堥珮閫熼�氫俊闇�姹傘��
銆�銆�5. 宓屽叆寮忕‖鏍� IP锛氬寘鎷� PCIe Endpoint銆佸崈鍏嗕互澶恫(w菐ng) MAC 绛夌‖鏍告ā濉婏紝娓涘皯闁嬬櫦(f膩)鏅傞枔鍜屾垚鏈�銆�
銆�銆�6. 鍙摯灞曟�у挤锛氶�氶亷 FPGA 鐨勯潏娲绘灦妲嬪彲浠ュ揩閫熻鏁磋ō瑷堟柟妗�锛屾豢瓒充笉鍚岄爡鐩渶姹傘��
銆�銆�7. 澶氱ó I/O 妯欐簴鏀寔锛氬吋瀹� LVCMOS銆丩VDS 绛夊绋俊铏熸婧�锛屼究浜庤垏澶栭儴瑷倷閫ｆ帴銆�
銆�銆�姝よ姱鐗囬仼鐢ㄤ簬闇�瑕侀珮鎬ц兘鍜岄珮搴﹂泦鎴愮殑鎳夌敤鍫存櫙銆�
XC5VLX50T-3FF665C 寤ｆ硾鎳夌敤浜庡鍊嬮牁鍩燂細
銆�銆�1. 閫氫俊鍩虹瑷柦锛氬鐒＄窔鍩虹珯銆佽矾鐢卞櫒銆佷氦鎻涙绛夎ō鍌欎腑鐨勪俊铏熻檿鐞嗗拰鍗�(xi茅)璀拌綁鎻涖��
銆�銆�2. 鍦栧儚鑸囪闋昏檿鐞嗭細鐢ㄤ簬瀵︽檪瑕栭牷绶ㄧ⒓瑙ｇ⒓銆佸湒鍍忓寮峰強鍒嗘瀽绛夐牁鍩�銆�
銆�銆�3. 閱�(y墨)鐧傛垚鍍忚ō鍌欙細鏀寔瓒呰伈娉�銆丆T 鎺冩弿鍎�绛夐啱(y墨)鐧傚剙鍣ㄧ殑鏁�(sh霉)鎿�(j霉)閲囬泦鍜岃檿鐞�銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栨帶鍒讹細瀵︾従(xi脿n)寰╅洔宸ユキ(y猫)绯荤当(t菕ng)涓殑閬嬪嫊鎺у埗鍜岄亷绋嬬洠(ji膩n)鎺�銆�
銆�銆�5. 娓│娓噺鍎�鍣細鎻愪緵绮剧⒑鐨勪俊铏熺敓鎴愬拰鍒嗘瀽鑳藉姏銆�
銆�銆�6. 楂樻�ц兘瑷堢畻锛氱敤浣滃崝(xi茅)铏曠悊鍣ㄥ姞閫熺壒瀹氱畻娉曢亱绠�銆�
銆�銆�鍏跺挤澶х殑鎬ц兘鍜屽鍔熻兘鎬т娇寰楀畠鎴愮偤鐪惧楂樻�ц兘闆诲瓙绯荤当(t菕ng)鐨勭悊鎯抽伕鎿�銆�
XC5VLX50T-2FF665C
銆�銆�XC5VLX50T-3FF676C
銆�銆�XC5VLX50T-3FG320C
