鏅傞枔锛�2025/5/16 15:25:08
闁辫畝锛�21
XC5VTX240T-1FF1759C 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-5 绯诲垪鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛團PGA锛夎姱鐗囥�傝┎绯诲垪 FPGA 浠ュ叾楂樻�ц兘銆侀珮闆嗘垚搴﹀拰闈堟椿鐨勬灦妲�(g貌u)鑰岃仦鍚嶏紝寤ｆ硾鎳夌敤浜庨�氫俊銆佷俊铏熻檿鐞嗐�佸湒鍍忚檿鐞嗗拰宓屽叆寮忕郴绲�(t菕ng)绛夐牁鍩�銆�
銆�銆�Virtex-5 FPGA 鍩轰簬鍏堥�茬殑 65nm 宸ヨ棟鎶�琛撳埗閫�锛屽叿鏈夎睈瀵岀殑閭忚集璩囨簮銆侀珮閫熶覆琛屾敹鐧�(f膩)鍣ㄥ拰 DSP Slice锛岃兘澶犳豢瓒冲京闆滆ō瑷堢殑闇�姹�銆俋C5VTX240T-1FF1759C 灞簬 Virtex-5 TX 绯诲垪锛岀壒鍒ラ仼鐢ㄤ簬闇�瑕侀珮甯跺涓茶閫氫俊鐨勬噳鐢ㄥ牬鏅�銆�
鍨嬭櫉锛歑C5VTX240T-1FF1759C
銆�銆�灏佽锛欶FG1759
銆�銆�宸ヨ棟鍒剁▼锛�65nm
銆�銆�閰嶇疆妯″紡锛歋electMAP 鍜� Master SPI
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 24 钀��
銆�銆�RAM 璩囨簮锛氱磩 13.6MB
銆�銆�DSP Slice 鏁�(sh霉)閲忥細960 鍊�
銆�銆�鐢ㄦ埗 I/O 鏁�(sh霉)閲忥細鏈�澶� 844 鍊�
銆�銆�鏅傞悩绠＄悊璩囨簮锛氭渶澶� 8 鍊� PLL
銆�銆�楂橀�熶覆琛屾敹鐧�(f膩)鍣細鏈�澶ф敮鎸� 24 鍊� GTP/GTX 鏀剁櫦(f膩)鍣紝閫熺巼鑼冨湇鐐� 600Mbps 鑷� 11.18Gbps
銆�銆�鍔熻�楋細鏍规摎(j霉)鎳夌敤涓嶅悓鍕曟厠(t脿i)瑾�(di脿o)鏁�
Virtex-5 TX 绯诲垪 FPGA 鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樻�ц兘鏋舵(g貌u)锛氬熀浜� 65nm 宸ヨ棟鍒堕��锛屾彁渚涘挤澶х殑閭忚集璩囨簮鍜岃▓绠楄兘鍔�銆�
銆�銆�2. 楂橀�熶覆琛屾敹鐧�(f膩)鍣細鏀寔楂橀仈 11.18Gbps 鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼锛岄仼鍚堥珮甯跺鎳夌敤鍫存櫙銆�
銆�銆�3. 寮峰ぇ鐨� DSP 鍔熻兘锛氬収(n猫i)缃皥鐢� DSP Slice锛屾敮鎸佸京闆滅殑鏁�(sh霉)瀛椾俊铏熻檿鐞嗕换鍕�銆�
銆�銆�4. 澶у閲忓瓨鍎茶硣婧愶細闆嗘垚浜嗗ぇ閲忕殑 Block RAM 鍜屽垎甯冨紡 RAM锛屾豢瓒虫暩(sh霉)鎿�(j霉)绶╂矕闇�姹�銆�
銆�銆�5. 闈堟椿鐨勬檪閻樼鐞嗭細閰嶅倷澶氬�� PLL 妯″锛屾敮鎸佸绋檪閻樺垎閰嶅拰鍚屾姗熷埗銆�
銆�銆�6. 鍙潬鎬ц垏瀹夊叏鎬э細鏀寔澶氱ó鍔熻兘瀹夊叏鐗规�у強鍔犲瘑閰嶇疆閬搁爡銆�
銆�銆�7. 寤ｆ硾鐨勬帴鍙ｆ敮鎸侊細鍏煎 PCIe銆乆AUI銆丆PRI 绛夊绋崝(xi茅)璀版婧栥��
XC5VTX240T-1FF1759C 鍦ㄥ鍊嬮牁鍩熸湁寤ｆ硾鎳夌敤锛屽寘鎷絾涓嶉檺浜庯細
銆�銆�1. 閫氫俊瑷倷锛氬鐒＄窔鍩虹珯銆佽矾鐢卞櫒銆佷氦鎻涙绛�锛岀敤浜庡鐝�(xi脿n)鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鐧�(f膩)鍜屼俊铏熻檿鐞�銆�
銆�銆�2. 瑕栭牷鑸囧湒鍍忚檿鐞嗭細鏀寔楂樻竻瑕栭牷绶ㄧ⒓瑙ｇ⒓銆佸湒鍍忓寮风瓑鍔熻兘銆�
銆�銆�3. 娓│娓噺鍎�鍣細鐢ㄤ綔淇¤櫉鐢熸垚鎴栨暩(sh霉)鎿�(j霉)閲囬泦鐨勬牳蹇冭檿鐞嗗櫒銆�
銆�銆�4. 閱�(y墨)鐧傞浕瀛愶細鍦ㄨ秴鑱叉尝鎴愬儚銆丆T 鎺冩弿绛夎ō鍌欎腑浣滅偤鏍稿績鎺у埗鍣�銆�
銆�銆�5. 宸ユキ(y猫)鑷嫊鍖栵細瀵︾従(xi脿n)寰╅洔鐨勬帶鍒剁畻娉曞拰瀵︽檪鏁�(sh霉)鎿�(j霉)铏曠悊銆�
銆�銆�6. 杌嶄簨鑸囪埅绌鸿埅澶╋細鐢ㄤ簬闆烽仈绯荤当(t菕ng)銆佽(w猫i)鏄熼�氫俊浠ュ強灏庤埅瑷倷涓��
XC5VTX240T-1FFG1735C
銆�銆�XC5VTX240T-1FFG1735I
銆�銆�XC5VTX240T-1FFG1759I
