XC6SLX150-3FGG484C 鏅�(sh铆)闁擄細2023/8/4 17:25:15 闁辫畝锛�421

鎻忚堪

鐢�(ch菐n)鍝佸瀷铏�(h脿o)	XC6SLX150-3FGG484C
鎻忚堪	IC FPGA 338 I/O 484FBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)
鐢熺敘(ch菐n)寤犲	Xilinx鍏徃
绯诲垪	Spartan?-6 LX
閮ㄥ垎鐙€鎱�(t脿i)	娲绘€�
闆诲-闆绘簮	1.14V~1.26V
宸ヤ綔婧害	0掳C~85掳C(TJ)
鍖�/绠�	484 BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘	484-FBGA(23x23)
鍩虹(ch菙)閮ㄤ欢铏�(h脿o)	XC6SLX150

鐢�(ch菐n)鍝佸湒鐗�

XC6SLX150-3FGG484C

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
绗﹀悎REACH妯�(bi膩o)婧�(zh菙n)	鏄�
绗﹀悎姝愮洘RoHS妯�(bi膩o)婧�(zh菙n)	鏄�
鐙€鎱�(t脿i)	娲绘€�
鏅�(sh铆)閻橀牷鐜�-鏈€澶у€�	862.0 MHz
CLB-Max鐨勭祫鍚堝欢閬�	0.21 ns
JESD-30浠ｇ⒓	S-PBGA-B484
JESD-609浠ｇ⒓	E1
绺絉AM浣嶆暩(sh霉)	4939776
CLB鏁�(sh霉)閲�	11519.0
杓稿叆鏁�(sh霉)閲�	338.0
閭忚集鍠厓鐨勬暩(sh霉)閲�	147443.0
杓稿嚭鏁�(sh霉)閲�	338.0
绲傜鏁�(sh霉)閲�	484
宸ヤ綔婧害-鏈€灏忓€�	0鈩�
宸ヤ綔婧害-鏈€楂�	85鈩�
绲勭箶	11519 CLBS
宄板€煎洖娴佹韩搴�(鈩�)	250
闆绘簮	1.2,2.5 / 3.3
璩囨牸鐙€鎱�(t脿i)	涓嶅悎鏍�
鍧愬Э楂樺害-鏈€澶�	2.6姣背
瀛愰鍒�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
闆绘簮闆诲	1.2 V
闆绘簮闆诲-鏈€灏忓€�	1.14 V
闆绘簮闆诲-鏈€澶у€�	1.26 V
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
婧害绛夌礆(j铆)	鍏朵粬
绲傜瀹屾垚	閷�/閵€/閵�(Sn96.5Ag3.0Cu0.5)
绲傜琛ㄦ牸	鐞�
绲傜闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅�(sh铆)闁揁宄板€煎洖娴佹韩搴�-鏈€澶у€�	涓夊崄
闀峰害	23.0姣背
瀵害	23.0姣背
鍖呰楂旀潗鏂�	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰９浠ｇ⒓	BGA
鍖呯瓑鍍�(ji脿)浠ｇ⒓	BGA484,22X22,40
鍖呰褰㈢媭	寤ｅ牬
鍖呰棰�(f膿ng)鏍�	缍�(w菐ng)鏍奸櫍鍒�
鍒堕€犲晢鍖呰瑾槑	23 X 23 MM锛�1 MM PITCH锛孡EAD FREE锛孎(xi脿n)BGA-484

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

鐒￠墰鐙€鎱�(t脿i)/RoHS鐙€鎱�(t脿i)	鐒￠墰/绗﹀悎RoHS妯�(bi膩o)婧�(zh菙n)
婵曞害鏁忔劅搴︾瓑绱�(j铆)(MSL)	3(168灏忔檪(sh铆))

鐗归粸(di菐n)

浜ら尟(cu貌)鐨勫
楂橀仈(d谩)3.2 Gb/s
鐔辨彃鎷斿悎瑕�(gu墨)鎬�
澶氬€�(g猫)楂樻晥鐨勯泦鎴愬
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楂樻晥鐨凞SP48A1鍒囩墖
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绨″寲閰嶇疆锛屾敮鎸佷綆鎴愭湰妯�(bi膩o)婧�(zh菙n)
浼戠湢鎺夐浕妯″紡锛屽(sh铆)鐝�(xi脿n)闆跺姛鑰�
Spartan-6 LX FPGA锛氶倧杓劒(y艒u)鍖�
澶у瀷瑷�(sh猫)鍌欎腑鐨凙ES姣旂壒娴佸姞瀵�
鐢ㄤ簬浣庢姈鍕�(d貌ng)鏅�(sh铆)閻樼殑閹栫浉鐠�(hu谩n)(PLL)
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蹇€�18 x 18涔樻硶鍣ㄥ拰48浣嶇疮鍔犲櫒
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澶氶浕澹擄紝澶氭(bi膩o)婧�(zh菙n)SelectIO?鎺ュ彛绲�
鍏锋湁瀛楃瘈(ji茅)瀵娇鑳界殑蹇€烞lock RAM
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鍙伕杓稿嚭椹�(q奴)鍕�(d貌ng)锛屾瘡鍊�(g猫)寮曡叧鏈€楂�24 mA
鍙伕鐨勭Щ浣嶅瘎瀛樺櫒鎴栧垎甯冨紡RAM鏀寔
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鍔熻兘璞愬瘜鐨刋ilinx Platform Flash鍜孞TAG
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鐢ㄤ簬PCI Express瑷�(sh猫)瑷�(j矛)鐨勯泦鎴愮榛�(di菐n)妯″(LXT)
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鏁�(sh霉)鎿�(j霉)閫熺巼楂橀仈(d谩)800 Mb / s(宄板€煎付瀵偤12.8 Gb/s)
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18 Kb濉�锛屽彲閬告搰绶ㄧ▼鐐哄叐鍊�(g猫)鐛�(d煤)绔嬬殑9 Kb Block RAM
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