鑺�鐗囧瀷铏�(h脿o)锛歑C6SLX16-2CSG324C
銆�銆�FPGA绯诲垪锛歋partan-6
銆�銆�鑺�鐗囧皝瑁濓細CSG324C
銆�銆�閭忚集鍠�鍏冩��(sh霉)閲忥細16,640
銆�銆�瀛樺劜(ch菙)鍠�鍏冩��(sh霉)閲忥細576Kb
銆�銆�绶氳矾寤舵檪(sh铆)锛�0.766 ns
銆�銆�鏈�澶у伐浣滈牷鐜囷細400 MHz
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