鍨嬭櫉(h脿o)锛歑C6SLX162FTG256I
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛歋partan-6
銆�銆�FPGA 閭忚集鍠�鍏冩��(sh霉)閲忥細162,000
銆�銆�濉婂瓨鍎�(ch菙)鍣ㄥ�归噺锛�1,836 Kb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細360
銆�銆�I/O 寮曡叧鏁�(sh霉)閲忥細256
銆�銆�宸ヤ綔闆诲�擄��1.2V 鏍稿績闆诲�擄��3.3V/2.5V/1.8V I/O 闆诲��
銆�銆�灏佽�濆舰寮忥細FTG256 (Fine Pitch BGA)
銆�銆�宸ヨ棟绡�(ji茅)榛�(di菐n)锛�45nm
銆�銆�鏈�澶х敤鎴跺彲鐢ㄥ瓨鍎�(ch菙)鍣�锛�9Mb
銆�銆�鏅�(sh铆)閻樼�＄悊璩囨簮锛�2 鍊�(g猫) PLL 鎴� 1 鍊�(g猫) PLL + 1 鍊�(g猫) DCM

XC6SLX162FTG256I 鎻愪緵浜嗗挤(qi谩ng)澶х殑纭�浠舵�ц兘鑸囬潏娲绘�э細
銆�銆�1. 楂樺瘑搴﹂倧杓�璩囨簮锛氭搧鏈夎秴閬�(gu貌) 16 钀�(w脿n)鍊�(g猫)閭忚集鍠�鍏�锛屽彲瀵�(sh铆)鐝�(xi脿n)寰�(f霉)闆滅殑鏁�(sh霉)瀛楅浕璺�鍔熻兘銆�
銆�銆�2. 澶氱ó瀛樺劜(ch菙)閬搁爡(xi脿ng)锛氬収(n猫i)缃� 1,836Kb 鐨勫�婂瓨鍎�(ch菙)鍣�锛岃兘澶犳豢瓒虫暩(sh霉)鎿�(j霉)绶╂矕鍜屾煡鎵捐〃绛夐渶姹�銆�
銆�銆�3. 楂樻晥 DSP 鏀�鎸侊細闆嗘垚浜� 360 鍊�(g猫) DSP Slice锛岀壒鍒ラ仼鍚堜俊铏�(h脿o)铏曠悊鍜岀畻娉曞姞閫熶换鍕�(w霉)銆�
銆�銆�4. 闈堟椿鐨� I/O 閰嶇疆锛氭敮鎸佸�氱ó妯�(bi膩o)婧�(zh菙n)鎺ュ彛鍗�(xi茅)璀�锛屼緥濡� LVCMOS銆丩VDS 鍜� SSTL銆�
銆�銆�5. 鍏�(n猫i)缃�鏅�(sh铆)閻樼�＄悊锛氬寘鎷� PLL 鍜� DCM 妯″�婏紝鍙�浠ョ敓鎴愮簿纰虹殑鏅�(sh铆)閻樹俊铏�(h脿o)銆�
銆�銆�6. 浣庡姛鑰楄ō(sh猫)瑷�(j矛)锛氶噰鐢ㄥ厛閫�(j矛n)鐨� 45nm 宸ヨ棟鎶�琛�(sh霉)锛屽湪淇濊瓑鎬ц兘鐨勫悓鏅�(sh铆)鍎�(y艒u)鍖栦簡鑳借�楄〃鐝�(xi脿n)銆�
銆�銆�7. 鏄撶敤闁嬬櫦(f膩)宸ュ叿锛氱祼(ji茅)鍚� Xilinx ISE Design Suite锛屾彁渚涘緸瑷�(sh猫)瑷�(j矛)杓稿叆鍒伴��(y脿n)璀夌殑涓�绔欏紡瑙ｆ焙鏂规�堛��
銆�銆�8. 鍙�闈犳�ч珮锛氬叿鍌欏叏闈㈢殑娓�(c猫)瑭﹀姛鑳藉拰鑷�鎴戣ê鏂疯兘鍔�锛岀⒑淇濈郴绲�(t菕ng)閬�(y霉n)琛岀┅(w臎n)瀹�銆�

XC6SLX162FTG256I 閬╃敤浜庝互涓嬪牬(ch菐ng)鏅�锛�
銆�銆�1. 宓屽叆寮忕郴绲�(t菕ng)瑷�(sh猫)瑷�(j矛)锛氫綔鐐烘牳蹇冭檿鐞嗗櫒鎴栧崝(xi茅)铏曠悊鍣ㄤ娇鐢ㄣ��
銆�銆�2. 瑕栭牷鑸囧湒鍍忚檿鐞嗭細鍒╃敤鍏� DSP Slice 瀵�(sh铆)鐝�(xi脿n)楂樿唱(zh矛)閲忚�栭牷绶ㄧ⒓瑙ｇ��銆�
銆�銆�3. 宸ユキ(y猫)鑷�鍕�(d貌ng)鍖栨帶鍒讹細璨�(f霉)璨�(z茅)瀵�(sh铆)鏅�(sh铆)鏁�(sh霉)鎿�(j霉)閲囬泦鍜岃檿鐞嗐��
銆�銆�4. 閫氫俊鍩虹��(ch菙)瑷�(sh猫)鏂斤細鐢ㄤ簬缍�(w菐ng)绲�(lu貌)浜ゆ彌姗�(j墨)銆佽矾鐢卞櫒绛夐棞(gu膩n)閸电祫浠�銆�
銆�銆�5. 閱�(y墨)鐧傛垚鍍忚ō(sh猫)鍌欙細鎻愪緵蹇�閫熷湒鍍忛噸寤哄拰鍒嗘瀽鑳藉姏銆�
銆�銆�6. 娑堣不(f猫i)椤為浕瀛愮敘(ch菐n)鍝侊細濡傞珮娓呴浕瑕栥�佹父鎴叉��(j墨)绛夐渶瑕佸挤(qi谩ng)澶ц▓(j矛)绠楀姏鐨勭敘(ch菐n)鍝�銆�
銆�銆�7. 娓�(c猫)瑭︽脯(c猫)閲�?j墨)x鍣�锛氭��(g貌u)寤鸿嚜瀹氱京淇¤櫉(h脿o)鐢熸垚鑸囬噰闆嗗钩鑷�(t谩i)銆�
銆�銆�姝ゆ�� FPGA 鐨勫�氬姛鑳芥�у拰鎿�(ku貌)灞曟�т娇鍏舵垚鐐虹溇澶氳�屾��(y猫)鐨勭悊鎯抽伕鎿�銆�

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