XC6SLX45-2CSG324I 鏅傞枔锛�2025/5/10 10:50:50 闁辫畝锛�26

XC6SLX45-2CSG324I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Spartan-6 绯诲垪 FPGA 鑺墖涓殑涓€鍊嬪瀷铏�銆係partan-6 绯诲垪鏄潰鍚戜綆鎴愭湰銆佷綆鍔熻€楁噳(y墨ng)鐢ㄧ殑 FPGA 骞宠嚭锛岄仼鍚堝伐妤�(y猫)鎺у埗銆佹秷璨�(f猫i)闆诲瓙銆侀€氫俊瑷�(sh猫)鍌欏拰姹借粖闆诲瓙绛夐牁(l菒ng)鍩熴€傝┎鍨嬭櫉閲囩敤 45nm 宸ヨ棟鍒堕€�锛屽叿鏈夎睈瀵岀殑閭忚集璩囨簮鍜� DSP Slice锛屽悓鏅傛敮鎸佸绋珮閫熸帴鍙�銆傛鍣ㄤ欢灏佽鐐� CSG锛圕eramic Column Grid Array锛�锛屽紩鑵虫暩(sh霉)鐐� 324銆�
銆€銆€XC6SLX45 灞簬 Spartan-6 LX 瀹舵棌锛屼富瑕侀潰鍚戜綆鍔熻€�銆侀珮鎬у児姣旂殑鎳�(y墨ng)鐢ㄥ牬鏅€傚叾鍏�(n猫i)閮ㄧ祼(ji茅)妲�(g貌u)鍖呮嫭鍙法绋嬮倧杓锛圕LB锛�銆丅lock RAM銆丏SP Slice 鍜屽皥鐢� IO 妯″锛岃兘澶犻潏娲诲(sh铆)鐝�(xi脿n)鍚勭ó鏁�(sh霉)瀛楅浕璺ō(sh猫)瑷�(j矛)銆�

鍙冩暩(sh霉)

鍨嬭櫉锛歑C6SLX45-2CSG324I
銆€銆€绯诲垪锛歋partan-6
銆€銆€瀹舵棌锛歀X
銆€銆€宸ヨ棟锛�45nm
銆€銆€閭忚集鍠厓鏁�(sh霉)閲忥細澶х磩 27,168 鍊� CLB 鍒囩墖
銆€銆€DSP Slice 鏁�(sh霉)閲忥細180 鍊�
銆€銆€RAM 璩囨簮锛氱磩 1.4Mb 鍒嗗竷寮� RAM 鍜� Block RAM
銆€銆€鐢ㄦ埗 I/O 寮曡叧锛氭渶澶� 236 鍊�
銆€銆€閰嶇疆妯″紡锛氬緸 Slave Serial (SPI)銆丮aster SelectMAP銆丅oundary Scan 绛�
銆€銆€宸ヤ綔闆诲锛氭牳蹇冮浕澹� 1.2V锛孖O 闆诲鏀寔 1.2V/1.5V/1.8V/2.5V/3.3V
銆€銆€閫熷害绛夌礆锛�-2锛堝皪鎳�(y墨ng)鐗瑰畾鏅傞悩闋荤巼鎬ц兘锛�
銆€銆€灏佽椤炲瀷锛欳SG324

鐗规€�

1. 楂樺害闆嗘垚锛歑C6SLX45 鎻愪緵璞愬瘜鐨勯倧杓硣婧愬拰宓屽叆寮忓瓨鍎插櫒妯″锛屾敮鎸佸京(f霉)闆滅畻娉曞拰鏁�(sh霉)鎿�(j霉)铏曠悊浠诲嫏(w霉)銆�
銆€銆€2. 浣庡姛鑰楄ō(sh猫)瑷�(j矛)锛氬熀浜� 45nm 宸ヨ棟锛岃姱鐗囧湪淇濊瓑鎬ц兘鐨勫悓鏅傚ぇ骞呴檷浣庡姛鑰�锛岀壒鍒ラ仼鍚堝皪鑳借€楁晱鎰熺殑鎳�(y墨ng)鐢ㄣ€�
銆€銆€3. 澶氱ó鎺ュ彛鏀寔锛氬収(n猫i)缃� PCI Express銆佸崈鍏嗕互澶恫(w菐ng)銆丏DR3 鎺у埗鍣ㄧ瓑纭牳妯″锛屼究浜庡揩閫熸(g貌u)寤虹郴绲�(t菕ng)绱氳В姹烘柟妗�銆�
銆€銆€4. 鍙摯(ku貌)灞曟€у挤(qi谩ng)锛氶€氶亷 Xilinx 鐨� EDK 鎴� Vivado 宸ュ叿閺堬紝鐢ㄦ埗鍙互杓曟澗娣诲姞澶栬ō(sh猫)鎴栧畾鍒跺姛鑳�銆�
銆€銆€5. 鎴愮啛鐨勭敓鎱�(t脿i)绯荤当(t菕ng)锛歑ilinx 鎻愪緵浜嗗畬鍠勭殑闁嬬櫦(f膩)鐠�(hu谩n)澧�锛屽 ISE Design Suite 鍜� Vivado锛屼互鍙婂ぇ閲忕殑鍙冭€冭ō(sh猫)瑷�(j矛)鍜� IP 鏍�锛岄檷浣庝簡闁嬬櫦(f膩)闁€妾�銆�
銆€銆€6. 楂樺彲闈犳€э細閬╃敤浜庡伐妤�(y猫)鍜屾苯杌婇牁(l菒ng)鍩�锛屽叿鍌欒壇濂界殑鎶楀共鎿捐兘鍔涘拰瀵韩鑼冨湇閬搁爡(xi脿ng)锛堥渶鍏烽珨纰鸿獚(r猫n)鏄惁閬稿瀷宸ユキ(y猫)绱氱増鏈級銆�

鎳�(y墨ng)鐢�

XC6SLX45-2CSG324I 甯哥敤浜庝互涓嬮牁(l菒ng)鍩燂細
銆€銆€1. 宸ユキ(y猫)鑷嫊鍖栵細閬�(y霉n)鍕曟帶鍒�銆佹(j墨)鍣ㄨ瑕�銆丳LC 绶ㄧ▼鎺у埗鍣�銆�
銆€銆€2. 閫氫俊瑷�(sh猫)鍌欙細鍩虹珯淇¤櫉铏曠悊銆佺恫(w菐ng)绲�(lu貌)浜ゆ彌姗�(j墨)銆佽矾鐢卞櫒銆�
銆€銆€3. 娑堣不(f猫i)椤為浕瀛愶細楂樻竻瑕栭牷铏曠悊銆佹父鎴叉(j墨)鍦栧舰鍔犻€�銆�
銆€銆€4. 姹借粖闆诲瓙锛欰DAS 杓斿姪椐曢绯荤当(t菕ng)銆佽粖杓変俊鎭妯傜郴绲�(t菕ng)銆�
銆€銆€5. 閱�(y墨)鐧傝ō(sh猫)鍌欙細瓒呰伈娉㈡垚鍍�銆侀啱(y墨)鐧傚剙鍣ㄦ暩(sh霉)鎿�(j霉)閲囬泦鑸囪檿鐞�銆�
銆€銆€6. 鍦嬮槻鑸囪埅澶╋細闆烽仈(d谩)淇¤櫉铏曠悊銆佸皫(d菐o)鑸郴绲�(t菕ng)銆佸姞瀵嗛€氫俊銆�