鏅傞枔锛�2023/8/4 17:25:00
闁辫畝锛�410
鐢�(ch菐n)鍝佸瀷铏� | XC6SLX45-3CSG484C |
鎻忚堪 | IC FPGA 320 I/O 484CSBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鐢熺敘(ch菐n)寤犲 | Xilinx鍏徃 |
绯诲垪 | Spartan?-6 LX |
閮ㄥ垎鐙�鎱�(t脿i) | 娲绘�� |
闆诲-闆绘簮 | 1.14V~1.26V |
宸ヤ綔婧害 | 0掳C~85掳C(TJ) |
鍖�/绠� | 484-FBGA锛孋SPBGA |
渚涙噳鍟嗚ō鍌欏寘 | 484-CSPBGA(19x19) |
鍩虹閮ㄤ欢铏� | XC6SLX45 |
XC6SLX45-3CSG484C
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
绗﹀悎REACH妯欐簴 | 鏄� |
绗﹀悎姝愮洘RoHS妯欐簴 | 鏄� |
鐙�鎱�(t脿i) | 娲绘�� |
鏅傞悩闋荤巼-鏈�澶у�� | 862.0 MHz |
CLB-Max鐨勭祫鍚堝欢閬� | 0.21 ns |
JESD-30浠ｇ⒓ | S-PBGA-B484 |
JESD-609浠ｇ⒓ | E1 |
绺絉AM浣嶆暩(sh霉) | 2138112 |
CLB鏁�(sh霉)閲� | 3411.0 |
杓稿叆鏁�(sh霉)閲� | 310.0 |
閭忚集鍠厓鐨勬暩(sh霉)閲� | 43661.0 |
杓稿嚭鏁�(sh霉)閲� | 310.0 |
绲傜鏁�(sh霉)閲� | 484 |
宸ヤ綔婧害-鏈�灏忓�� | 0鈩� |
宸ヤ綔婧害-鏈�楂� | 85鈩� |
绲勭箶 | 3411 CLBS |
宄板�煎洖娴佹韩搴�(鈩�) | 260 |
闆绘簮 | 1.2,2.5 / 3.3 |
璩囨牸鐙�鎱�(t脿i) | 涓嶅悎鏍� |
鍧愬Э楂樺害-鏈�澶� | 1.8姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲 | 1.2 V |
闆绘簮闆诲-鏈�灏忓�� | 1.14 V |
闆绘簮闆诲-鏈�澶у�� | 1.26 V |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛� | CMOS |
婧害绛夌礆 | 鍏朵粬 |
绲傜瀹屾垚 | 閷�/閵�/閵�(閷�/閵�/閵�) |
绲傜琛ㄦ牸 | 鐞� |
绲傜闁撹窛 | 0.8姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅傞枔@宄板�煎洖娴佹韩搴�-鏈�澶у�� | 涓夊崄 |
闀峰害 | 19.0姣背 |
瀵害 | 19.0姣背 |
鍖呰楂旀潗鏂� | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰９浠ｇ⒓ | FBGA |
鍖呯瓑鍍逛唬纰� | BGA484,22X22,32 |
鍖呰褰㈢媭 | 寤ｅ牬 |
鍖呰棰ㄦ牸 | 缍�(w菐ng)鏍奸櫍鍒楋紝绮剧窗闁撹窛 |
鍒堕�犲晢鍖呰瑾槑 | 19 X 19 MM锛�0.80 MM PITCH锛岀劇閴�锛孊GA-484 |
鐒￠墰鐙�鎱�(t脿i)/RoHS鐙�鎱�(t脿i) | 鐒￠墰/绗﹀悎RoHS妯欐簴 |
婵曞害鏁忔劅搴︾瓑绱�(MSL) | 3(168灏忔檪) |
浜ら尟鐨勫
楂橀仈3.2 Gb /s
灏堢偤浣庢垚鏈�岃ō瑷�
澶氬�嬮珮鏁堢殑闆嗘垚濉�
鍎�(y艒u)鍖栫殑I / O妯欐簴閬告搰
澶ф壒閲忓鏂欑窔鐒婂寘瑁�
闈滄厠(t脿i)鍜屽嫊鎱�(t脿i)鍔熺巼浣�
鐔辨彃鎷斿悎瑕�(gu墨)鎬�
楂樻晥鐨凞SP48A1鍒囩墖
娴佹按绶氬拰绱氳伅(li谩n)鍔熻兘
闆嗘垚鍏�(n猫i)瀛樻帶鍒跺櫒濉�
2閲濊嚜鍕曟娓厤缃�
浣庡櫔闊�锛岄潏娲荤殑鏅傞悩
楂樻�ц兘绠楄鍜屼俊铏熻檿鐞�
澧炲挤浜嗚ō瑷堜繚璀风殑瀹夊叏鎬�
妤�(y猫)鐣岄牁鍏堢殑IP鍜屽弮鑰冭ō瑷�
3.3V鑷�1.2VI / O妯欐簴鍜屽崝(xi茅)璀�
鍗佸叚鍊嬩綆鍋忕Щ鍏ㄥ眬鏅傞悩缍�(w菐ng)绲�
绨″寲閰嶇疆锛屾敮鎸佷綆鎴愭湰妯欐簴
Block RAM鍏锋湁寤ｆ硾鐨勭矑搴�
浼戠湢鎺夐浕妯″紡锛屽鐝�(xi脿n)闆跺姛鑰�
Spartan-6 LX FPGA锛氶倧杓劒(y艒u)鍖�
澶у瀷瑷倷涓殑AES姣旂壒娴佸姞瀵�
鏅傞悩绠＄悊骞抽嫪(CMT)浠ユ彁楂樻�ц兘
鐢ㄤ簬浣庢姈鍕曟檪閻樼殑閹栫浉鐠�(hu谩n)(PLL)
浣庢垚鏈琀STL鍜孲STL瀛樺劜鍣ㄦ帴鍙�
蹇��18 x 18涔樻硶鍣ㄥ拰48浣嶇疮鍔犲櫒
闋愬姞娉曞櫒浠ュ崝(xi茅)鍔╅亷婵惧櫒鎳夌敤绋嬪簭
澶氶浕澹擄紝澶氭婧朣electIO?鎺ュ彛绲�
鍏锋湁瀛楃瘈(ji茅)瀵娇鑳界殑蹇�烞lock RAM
璞愬瘜鐨勯倧杓硣婧愬拰鏇撮珮鐨勯倧杓閲�
DDR锛孌DR2锛孌DR3鍜孡PDDR鏀寔
LXT FPGA涓殑楂橀�烥TP涓茶鏀剁櫦(f膩)鍣�
鍙伕鐨勭Щ浣嶅瘎瀛樺櫒鎴栧垎甯冨紡RAM鏀寔
鍔熻兘璞愬瘜鐨刋ilinx Platform Flash鍜孞TAG
鐢ㄤ簬瑷▓椹楄瓑鐨勫敮涓�瑷倷DNA妯欒瓨绗�
鍙伕杓稿嚭椹�(q奴)鍕�锛屾瘡鍊嬪紩鑵虫渶楂�24 mA
鍏锋湁鍚屾檪涔樻硶锛岄櫎娉曞拰鐩哥Щ鐨勯牷鐜囧悎鎴�
鍏锋湁闆欒Ц鐧�(f膩)鍣ㄧ殑LUT鐢ㄤ簬绠￠亾涓績鎳夌敤
45绱嶇背宸ヨ棟閲濆皪鎴愭湰鍜屼綆鍔熻�楅�茶浜嗗劒(y艒u)鍖�
鍙(di脿o)绡�(ji茅)鐨処 / O杞�(zhu菐n)鎻涢�熺巼鍙彁楂樹俊铏熷畬鏁存��
鐢ㄤ簬PCI Express瑷▓鐨勯泦鎴愮榛炴ā濉�(LXT)
寤ｆ硾鐨勭涓夋柟SPI(鏈�楂榵4)鍜孨OR闁冨瓨鏀寔
姣忓�嬪樊鍒咺 / O鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼楂橀仈1,080 Mb /s
鏁�(sh霉)鎿�(j霉)閫熺巼楂橀仈800 Mb / s(宄板�煎付瀵偤12.8 Gb /s)
浣庢垚鏈琍CI?鎶�琛撴敮鎸佸吋瀹�33 MHz锛�32浣嶅拰64浣嶈(gu墨)鑼�
楂樻晥鐨�6杓稿叆LUT鍙彁楂樻�ц兘骞舵渶澶ч檺搴﹀湴闄嶄綆鍔熻��
18 Kb濉�锛屽彲閬告搰绶ㄧ▼鐐哄叐鍊嬬崹绔嬬殑9 Kb Block RAM
鏁�(sh霉)瀛楁檪閻樼鐞嗗櫒(DCM)娑堥櫎浜嗘檪閻樺亸宸拰鍗犵┖姣斿け鐪�
鍏锋湁鐛ㄧ珛FIFO鐨勫绔彛绺界窔绲�(ji茅)妲�(g貌u)鍙笡灏戣ō瑷堟檪搴忓晱椤�
MultiBoot鏀寔浣跨敤鐪嬮杸鐙椾繚璀烽�茶澶氭瘮鐗规祦鐨勯仩绋嬪崌绱�
鎺涜捣妯″紡閫氶亷澶氬紩鑵冲枤閱�锛屾帶鍒跺寮蜂締缍寔鐙�鎱�(t脿i)鍜岄厤缃�
閫氶亷澧炲挤鐨勪綆鎴愭湰MicroBlaze?杌熻檿鐞嗗櫒瀵︾従(xi脿n)鏇村揩鐨勫祵鍏ュ紡铏曠悊
楂橀�熸帴鍙ｅ寘鎷細涓茶ATA锛孉urora锛�1G浠ュお缍�(w菐ng)锛孭CI Express锛孫BSAI锛孋PRI锛孍PON锛孏PON锛孌isplayPort鍜孹AUI
XC6SLX45-3CSG484C绗﹁櫉
XC6SLX45-3CSG484C鑵冲嵃
