鏅傞枔锛�2025/4/29 14:53:22
闁辫畝锛�30
XC6SLX45-N3FGG484I 鏄� Xilinx 鍏徃 Spartan-6 绯诲垪 FPGA 鐨勪竴绋瀷铏�銆係partan-6 FPGA 闈㈠悜浣庢垚鏈�銆佷綆鍔熻�楁噳鐢ㄨō(sh猫)瑷堬紝閬╃敤浜庡悇绋伐妤�(y猫)銆侀�氫俊鍜屾秷璨婚闆诲瓙闋�(l菒ng)鍩�銆傝┎绯诲垪鍩轰簬 45nm 宸ヨ棟鎶�琛�(sh霉)锛屾彁渚涗簡璞愬瘜鐨勯倧杓硣婧�銆佸祵鍏ュ紡瀛樺劜鍣ㄥ鍜� DSP 濉婏紝鏀寔闈堟椿鐨� I/O 妯欐簴閰嶇疆銆�
銆�銆�XC6SLX45 鏄� Spartan-6 绯诲垪涓殑涓瓑瑕�(gu墨)妯″櫒浠�锛屽叿鏈夎壇濂界殑鎬у児姣�锛岄仼鍚堥渶瑕佷竴瀹氶倧杓京闆滃害浣嗗皪鎴愭湰鏁忔劅鐨勬噳鐢ㄥ牬鏅�銆�
閭忚集鍠厓锛圫lice锛夛細27,168
銆�銆�Block RAM锛�1,080 Kb
銆�銆�DSP Slice锛�120
銆�銆�I/O 鏁�(sh霉)閲忥細332
銆�銆�閰嶇疆妯″紡锛歋electMAP銆丮aster SPI銆丼lave SPI銆丅oundary Scan
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�灏佽椤炲瀷锛欶GG484
銆�銆�鏍稿績闆诲锛�1.2V
銆�銆�I/O 闆诲锛�1.8V銆�2.5V銆�3.3V
XC6SLX45-N3FGG484I 鎻愪緵浜嗛珮鎬ц兘鐨勯倧杓檿鐞嗚兘鍔涳紝鍚屾檪鍏奸¨浜嗕綆鍔熻�楃壒鎬�銆傚叾鍏�(n猫i)閮ㄦ灦妲�(g貌u)鍖呮嫭鍙法绋嬮倧杓锛圕LB锛夈�佸垎甯冨紡 RAM銆丅lock RAM 鍜� DSP Slice锛岃兘澶�?q奴)宕縁(xi脿n)寰╅洔鐨勬暩(sh霉)瀛椾俊铏熻檿鐞嗗姛鑳�銆�
銆�銆�瑭茶姱鐗囬倓闆嗘垚浜嗗绋‖鏍告ā濉�锛屼緥濡傛檪閻樼鐞嗗柈鍏冿紙DCM 鍜� PLL锛�锛屼互鍙婂皥鐢ㄧ殑閰嶇疆鍜岃(di脿o)瑭︽帴鍙�銆�
銆�銆�Spartan-6 绯诲垪 FPGA 鐨勪竴澶х壒榛炴槸鍏跺壍(chu脿ng)鏂扮殑鍏╃礆浜掕伅(li谩n)鏋舵(g貌u)锛屽寘鎷� Switch Matrix 鍜� Dedicated Interconnect锛岄�欑ó绲�(ji茅)妲�(g貌u)鎻愰珮浜嗘�ц兘骞堕檷浣庝簡寤堕伈銆�
銆�銆�姝ゅ锛孹C6SLX45 鏀寔澶氱ó宸ユキ(y猫)妯欐簴鎺ュ彛鍗�(xi茅)璀�锛屽 PCIe銆丏DR3銆佸崈鍏嗕互澶恫(w菐ng)绛�锛岄潪甯搁仼鍚堥�氫俊銆佽闋昏檿鐞嗗拰宓屽叆寮忔帶鍒剁瓑鎳夌敤鍫存櫙銆�
XC6SLX45-N3FGG484I 寤ｆ硾鎳夌敤浜庝互涓嬮牁(l菒ng)鍩燂細
銆�銆�1. 宸ユキ(y猫)鑷嫊鍖栬垏鎺у埗锛氱敤浜庢暩(sh霉)鎿�(j霉)閲囬泦銆侀亱鍕曟帶鍒�銆佸湒鍍忚檿鐞嗙瓑浠诲嫏銆�
銆�銆�2. 閫氫俊瑷�(sh猫)鍌欙細閬╃敤浜庣劇绶氬熀绔�銆佺恫(w菐ng)绲′氦鎻涙鍜屽叾浠栭�氫俊鍩虹(ch菙)瑷�(sh猫)鏂�銆�
銆�銆�3. 娑堣不椤為浕瀛愮敘(ch菐n)鍝侊細濡傞珮娓呰闋昏檿鐞嗐�佹暩(sh霉)纰肩浉姗�銆佹父鎴叉绛夈��
銆�銆�4. 閱�(y墨)鐧傝ō(sh猫)鍌欙細濡傝秴鑱叉尝鎴愬儚銆佹偅鑰呯洠(ji膩n)璀风郴绲�(t菕ng)绛夈��
銆�銆�5. 杌婅級闆诲瓙锛氱敤浜庨椐涜紨鍔╃郴绲�(t菕ng)銆佽粖杓変俊鎭妯傜郴绲�(t菕ng)绛�銆�
銆�銆�瑭� FPGA 閭勮鐢ㄤ綔鍘熷瀷椹楄瓑骞宠嚭锛屽湪 ASIC 瑷�(sh猫)瑷堝垵鏈熸彁渚涘揩閫熻凯浠ｈ兘鍔�銆�
XC6SLX45T-FGG484C, XC6SLX45T-FGG484I
