鍨嬭櫉(h脿o)锛歑C6SLX75-3FGG484C
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛歋partan-6
銆�銆�瀛愮郴鍒楋細LX
銆�銆�FPGA瀹归噺锛�75K Logic Cells
銆�銆�閰嶇疆闁冨瓨锛氱劇(w煤)鍏�(n猫i)閮ㄩ杻瀛�锛岄渶澶栨帴閰嶇疆鑺�鐗�
銆�銆�I/O鏁�(sh霉)閲忥細328
銆�銆�DSP Slices锛�180
銆�銆�Block RAM锛氱磩1.3MB
銆�銆�閫熷害绛夌礆(j铆)锛�-3
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏細鍟嗘��(y猫)绱�(j铆)锛�0掳C 鑷� 95掳C锛�
銆�銆�灏佽�濆舰寮忥��484寮曡叧 FGG (Fine-Pitch Ball Grid Array)
銆�銆�渚涢浕闆诲�擄細鏍稿績闆诲��1.2V锛岃紨鍔╅浕澹�2.5V/3.3V

XC6SLX75-3FGG484C鍏峰倷楂樺害鐨勯潏娲绘�у拰寮�(qi谩ng)澶х殑铏曠悊鑳藉姏銆傚畠鏀�鎸佸�氱ó鏅�(sh铆)閻樼�＄悊鎶�琛�(sh霉)锛屽寘鎷�闆嗘垚鐨凞CM锛圖igital Clock Manager锛夊拰PLL锛圥hase-Locked Loop锛�锛屽彲瀵�(sh铆)鐝�(xi脿n)绮剧⒑鐨勬檪(sh铆)閻樺垎閰嶅拰闋荤巼鍚堟垚銆�
銆�銆�姝ゅ��锛岃┎鍣ㄤ欢閭勬彁渚涗簡璞愬瘜鐨勬帴鍙ｆ敮鎸�锛屽�傞珮閫熷樊鍒咺/O妯�(bi膩o)婧�(zh菙n)锛圠VDS銆乵ini-LVDS绛夛級銆丳CI Express Endpoint纭�鏍�銆佸崈鍏嗕互澶�缍�(w菐ng)纭�鏍哥��锛屼娇鍏堕潪甯搁仼鍚堥渶瑕侀珮鎬ц兘鏁�(sh霉)鎿�(j霉)鍌宠几?sh霉)鑶�?y墨ng)鐢ㄥ牬(ch菐ng)鏅�銆�
銆�銆�鍦ㄩ枊鐧�(f膩)宸ュ叿鏂归潰锛孹ilinx鎻愪緵ISE Design Suite浣滅偤閰嶅�楄粺浠讹紝鏀�鎸佸緸RTL浠ｇ⒓绶ㄥ��鍒版渶绲備綅娴佺敓鎴愮殑瀹屾暣瑷�(sh猫)瑷�(j矛)娴佺▼銆傚悓鏅�(sh铆)锛岄�氶亷(gu貌)浣跨敤ChipScope Pro绛夎��(di脿o)瑭﹀伐鍏�锛岀敤鎴跺彲浠ュ揩閫熷畾浣嶅拰瑙ｆ焙瑷�(sh猫)瑷�(j矛)涓�鐨勫��(w猫n)椤�銆�
銆�銆�瑭插櫒浠跺叿鏈夎純浣庣殑闈滄厠(t脿i)鍔熻�楀拰鍕�(d貌ng)鎱�(t脿i)鍔熻��锛岀壒鍒ラ仼鍚堝皪(du矛)鍔熻�楁晱鎰熺殑鎳�(y墨ng)鐢ㄥ牬(ch菐ng)鍚�銆傚叾闈堟椿鐨勫姛鑰楃�＄悊妯″紡鍏佽ū鐢ㄦ埗鏍规��(j霉)瀵�(sh铆)闅涢渶姹傝��(di脿o)鏁村伐浣滅媭鎱�(t脿i)锛岄��(j矛n)涓�姝ュ劒(y艒u)鍖栫郴绲�(t菕ng)鑳芥晥銆�

XC6SLX75-3FGG484C寤ｆ硾鎳�(y墨ng)鐢ㄤ簬鍚勭ó涓�绔�寰�(f霉)闆滃害鐨勬暩(sh霉)瀛椾俊铏�(h脿o)铏曠悊鍜屾帶鍒堕牁(l菒ng)鍩�銆傚吀鍨嬫噳(y墨ng)鐢ㄥ牬(ch菐ng)鏅�鍖呮嫭浣嗕笉闄愪簬锛�
銆�銆�1. 宸ユキ(y猫)鑷�鍕�(d貌ng)鍖栬垏鎺у埗锛氱敤浜庨亱(y霉n)鍕�(d貌ng)鎺у埗鍣�銆丳LC锛堝彲绶ㄧ▼閭忚集鎺у埗鍣�锛�銆佹��(j墨)鍣ㄤ汉鎺у埗绯荤当(t菕ng)绛夈��
銆�銆�2. 瑕栭牷鑸囧湒鍍忚檿鐞嗭細瀵�(sh铆)鐝�(xi脿n)瀵�(sh铆)鏅�(sh铆)瑕栭牷绶ㄧ⒓瑙ｇ⒓銆佸湒鍍忓�炲��(qi谩ng)銆佹ā寮忚瓨(sh铆)鍒ョ瓑鍔熻兘銆�
銆�銆�3. 閫氫俊瑷�(sh猫)鍌欙細閬╃敤浜庡熀甯惰檿鐞嗗柈鍏�銆佸皬鍨嬪熀绔�銆佺劇(w煤)绶氭帴鍏ラ粸(di菐n)绛�銆�
銆�銆�4. 娑堣不(f猫i)椤為浕瀛愮敘(ch菐n)鍝侊細濡傞珮绔�椤�绀鸿ō(sh猫)鍌�銆佹父鎴叉��(j墨)鍦栧舰鍔犻�熷崱绛�銆�銆�銆�6. 姹借粖闆诲瓙锛氶珮绱�(j铆)椐曢�涜紨鍔╃郴绲�(t菕ng)锛圓DAS锛�銆佽粖杓変俊鎭�濞涙��(l猫)绯荤当(t菕ng)鐨勪俊铏�(h脿o)铏曠悊鍠�鍏�銆�

XC6SLX75T-3FGG484C
銆�銆�XC6SLX75-2FGG484C
銆�銆�XC6SLX75-3FTG256C