鍨嬭櫉(h脿o)锛歑C6SLX75T-2CSG484I
銆�銆�绯诲垪锛歋partan-6
銆�銆�灏佽�濓細CSG484
銆�銆�閫熷害绛夌礆(j铆)锛�-2
銆�銆�閰嶇疆闁冨瓨锛氫笉闆嗘垚
銆�銆�閭忚集鍠�鍏冩��(sh霉)閲忥細75K
銆�銆�RAM 瀹归噺锛�139Kb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細160鍊�(g猫)
銆�銆�I/O 鏁�(sh霉)閲忥細334鍊�(g猫)
銆�銆�宸ヤ綔闆诲�擄��1.2V 鏍稿績闆诲��锛�1.5V/1.8V/2.5V/3.3V I/O 闆诲��
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��-40掳C 鑷� +85掳C 鍟嗘キ(y猫)绱�(j铆)

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銆�銆�1. 楂樻�ц兘閭忚集绲�(ji茅)妲�(g貌u)锛氬熀浜庢煡鎵捐〃锛圠UT锛夌殑鏋舵��(g貌u)锛屾彁渚涢珮閬�(d谩) 75,000 鍊�(g猫)閭忚集鍠�鍏�锛屾敮鎸佸京(f霉)闆滅殑鏁�(sh霉)瀛椾俊铏�(h脿o)铏曠悊浠诲嫏(w霉)銆�
銆�銆�2. 宓屽叆寮忓瓨鍎�(ch菙)鍣ㄥ�婏細鍏�(n猫i)缃� 139Kb 鐨� Block RAM锛屽彲鐢ㄤ簬鏁�(sh霉)鎿�(j霉)绶╂矕銆丗IFO 鍜屽叾浠栧瓨鍎�(ch菙)闇�姹�銆�
銆�銆�3. DSP Slice 鏀�鎸侊細鍖呭�� 160 鍊�(g猫) DSP Slice锛岃兘澶犲姞閫熶箻娉曠疮鍔犵瓑閬�(y霉n)绠�锛岄仼鍚堥煶闋�銆佽�栭牷鍜岄�氫俊闋�(l菒ng)鍩�銆�
銆�銆�4. 澶氭ǎ鍖栫殑 I/O 閰嶇疆锛氭敮鎸佸�氱ó妯�(bi膩o)婧�(zh菙n)鎺ュ彛鍗�(xi茅)璀帮紝濡� PCIe銆丏DR2/3銆丩VDS 绛�锛屾豢瓒充笉鍚屾噳(y墨ng)鐢ㄥ牬(ch菐ng)鏅�鐨勯渶姹�銆�
銆�銆�5. 鍏�(n猫i)閮ㄦ檪(sh铆)閻樼�＄悊锛氶泦鎴� PLL 鍜� DCM 妯″��锛屽彲鐢熸垚绮剧⒑鐨勬檪(sh铆)閻樹俊铏�(h脿o)浠ラ﹨(q奴)鍕�(d貌ng)鍏�(n猫i)閮ㄩ倧杓�銆�
銆�銆�6. 鍙�闈犳�ц垏浣庡姛鑰楋細閲囩敤鍏堥��(j矛n)鐨� 45nm 宸ヨ棟鍒剁▼锛屽叿鍌欏嫊(d貌ng)鎱�(t脿i)鍔熻�楄��(di脿o)绡�(ji茅)鍔熻兘锛岄檷浣庢暣楂旂郴绲�(t菕ng)鑳借��銆�
銆�銆�7. 鏄撲簬浣跨敤鐨勮ō(sh猫)瑷�(j矛)宸ュ叿锛氭敮鎸� Xilinx ISE Design Suite 鎴� Vivado Design Suite锛岀啊(ji菐n)鍖栭枊(k膩i)鐧�(f膩)娴佺▼銆�

瑭茶姱鐗囬仼鐢ㄤ簬澶氱ó琛屾キ(y猫)鍜岄牁(l菒ng)鍩�锛屽吀鍨嬫噳(y墨ng)鐢ㄥ寘鎷�锛�
銆�銆�1. 瑕栭牷鍜屽湒鍍忚檿鐞嗭細渚嬪�傞珮娓呮敐鍍忔��(j墨)銆侀’绀哄櫒鎺у埗鍣ㄧ瓑銆�
銆�銆�2. 閫氫俊瑷�(sh猫)鍌欙細濡傚皬鍨嬪熀绔�銆佺恫(w菐ng)绲�(lu貌)浜ゆ彌姗�(j墨)銆佽矾鐢卞櫒绛�銆�
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銆�銆�4. 娑堣不(f猫i)椤為浕瀛愮敘(ch菐n)鍝侊細澶氬獟楂旀挱鏀惧櫒銆佹父鎴叉��(j墨)閰嶄欢绛�銆�
銆�銆�5. 閱�(y墨)鐧傝ō(sh猫)鍌欙細瓒呰伈娉㈣ō(sh猫)鍌�銆佷究鏀滃紡瑷烘柗鍎�鍣ㄧ瓑銆�
銆�銆�6. 宓屽叆寮忚▓(j矛)绠楀钩鑷�(t谩i)锛氫綔鐐哄崝(xi茅)铏曠悊鍣ㄦ垨涓绘帶鍠�鍏冮��(y霉n)琛屽��(sh铆)鏅�(sh铆)鎿嶄綔绯荤当(t菕ng)銆�

XC6SLX75T-3CSG484C,XC6SLX75T-3FTG256C