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闁辫畝锛�34
XC6SLX9-3FT256C 鏄� Xilinx 鍏徃 Spartan-6 绯诲垪 FPGA 鐨勪竴绋瀷铏�銆傝┎鍣ㄤ欢閲囩敤 40nm 宸ヨ棟鍒堕��锛屽叿鏈夐珮鎬ц兘銆佷綆鍔熻�楃殑鐗归粸锛岄仼鐢ㄤ簬鍚勭ó宓屽叆寮忔噳鐢ㄥ拰鏁�(sh霉)瀛椾俊铏熻檿鐞嗛牁鍩熴��
銆�銆�Spartan-6 绯诲垪 FPGA 鎻愪緵浜嗛潏娲荤殑閭忚集绲愭鍜岃睈瀵岀殑 I/O 璩囨簮锛岃兘澶犳豢瓒冲緸娑堣不椤為浕瀛愮敘鍝佸埌宸ユキ(y猫)鎺у埗绛夊绋噳鐢ㄩ渶姹�銆俋C6SLX9 鏄┎绯诲垪涓純灏忚(gu墨)妯＄殑涓�娆�锛岄仼鍚堝皪鎴愭湰鏁忔劅涓旈渶瑕佷竴瀹氶倧杓硣婧愮殑鎳夌敤鍫存櫙銆�
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銆�銆�閰嶇疆闁冨瓨锛氱劇鐗囦笂闁冨瓨锛岄渶澶栫疆閰嶇疆鑺墖
銆�銆�I/O 寮曡叧鏁�(sh霉)锛�170
銆�銆�鏈�澶х敤鎴� I/O锛�144
銆�銆�瀛樺劜鍣ㄨ硣婧愶細18Kb Block RAM锛�132
銆�銆�DSP Slice锛�16
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�灏佽褰㈠紡锛欶T256
銆�銆�閫熷害绛夌礆锛�-3
XC6SLX9-3FT256C 鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 鏀寔澶氱ó閰嶇疆妯″紡锛屽涓诲緸 SPI銆丅PI 鍜� PROM 妯″紡銆�
銆�銆�2. 鍏х疆 DSP48A1 鐗囦笂涔樻硶鍣�/鍔犳硶鍣紝鐢ㄤ簬楂樻晥瀵︾従(xi脿n)鏁�(sh霉)瀛椾俊铏熻檿鐞嗗姛鑳�銆�
銆�銆�3. 闆嗘垚 SelectIO 鎶�琛�锛屾敮鎸侀珮閬� 3.3V 鐨� I/O 妯欐簴锛屽苟鍏煎澶氱ó鎺ュ彛鍗�(xi茅)璀�銆�
銆�銆�4. 鏀寔宓屽叆寮忚檿鐞嗗櫒纭牳妯″ MicroBlaze锛屽彲鐢ㄤ簬闁嬬櫦(f膩)杌熺‖浠跺崝(xi茅)鍚岃ō瑷�銆�
銆�銆�5. 鍏ч儴鏅傞悩绠＄悊鍠厓 DCM锛圖igital Clock Manager锛夊拰 PLL锛圥hase-Locked Loop锛夛紝鎻愪緵闈堟椿鐨勬檪閻樺垎閰嶈垏闋荤巼鍚堟垚鑳藉姏銆�
銆�銆�6. 杓冧綆鐨勯潨鎱�(t脿i)鍔熻�楋紝闈炲父閬╁悎渚挎敎寮忚ō鍌欐垨灏嶈兘鏁堟湁瑕佹眰鐨勬噳鐢�銆�
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XC6SLX9-3FT256C 甯哥敤浜庝互涓嬫噳鐢ㄥ牬鏅細
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銆�銆�5. 娑堣不椤為浕瀛愮敘鍝佺殑鍦栧舰鍔犻�熸垨鍦栧儚铏曠悊銆�
銆�銆�6. 鍚勭ó灏忓瀷鍖栦絾闇�瑕佸彲绶ㄧ▼閭忚集鐨勬噳鐢紝濡傛鍣ㄤ汉鎺у埗銆佽嚜鍕曞寲绯荤当(t菕ng)銆�
XC6SLX9-2FT256C
銆�銆�XC6SLX9-3CSG324C
銆�銆�XC6SLX9-3CPG196C
