鏅傞枔锛�2023/8/4 17:53:08
闁辫畝锛�615
鐢�(ch菐n)鍝佸瀷铏� | XC6VLX130T-2FF1156C |
鎻忚堪 | IC FPGA 600 I/O 1156FCBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鐢熺敘(ch菐n)寤犲 | Xilinx鍏徃 |
绯诲垪 | Virtex?-6 LXT |
閮ㄥ垎鐙�鎱�(t脿i) | 娲绘�� |
闆诲-闆绘簮 | 0.95V~1.05V |
宸ヤ綔婧害 | 0掳C~85掳C(TJ) |
鍖�/绠� | 1156-BBGA锛孎(xi脿n)CBGA |
渚涙噳鍟嗚ō鍌欏寘 | 1156-FCBGA(35x35) |
鍩虹閮ㄤ欢铏� | XC6VLX130T |
XC6VLX130T-2FF1156C
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
绗﹀悎REACH妯欐簴 | 鏄� |
鐙�鎱�(t脿i) | 娲绘�� |
鏅傞悩闋荤巼-鏈�澶у�� | 1286.0 MHz |
CLB-Max鐨勭祫鍚堝欢閬� | 4.29 ns |
JESD-30浠ｇ⒓ | S-PBGA-B1156 |
JESD-609浠ｇ⒓ | E0 |
绺絉AM浣嶆暩(sh霉) | 9732096 |
杓稿叆鏁�(sh霉)閲� | 600.0 |
閭忚集鍠厓鐨勬暩(sh霉)閲� | 128000.0 |
杓稿嚭鏁�(sh霉)閲� | 600.0 |
绲傜鏁�(sh霉)閲� | 1156 |
宸ヤ綔婧害-鏈�灏忓�� | 0鈩� |
宸ヤ綔婧害-鏈�楂� | 85鈩� |
宄板�煎洖娴佹韩搴�(鈩�) | 鏈鏄� |
闆绘簮 | 1,1.2 / 2.5 |
璩囨牸鐙�鎱�(t脿i) | 涓嶅悎鏍� |
鍧愬Э楂樺害-鏈�澶� | 3.5姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲 | 1.0 V |
闆绘簮闆诲-鏈�灏忓�� | 0.95 V |
闆绘簮闆诲-鏈�澶у�� | 1.05 V |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛� | CMOS |
婧害绛夌礆 | 鍏朵粬 |
绲傜瀹屾垚 | 閷�/閴�(Sn63Pb37) |
绲傜琛ㄦ牸 | 鐞� |
绲傜闁撹窛 | 1.0姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅傞枔@宄板�煎洖娴佹韩搴�-鏈�澶у��(s) | 鏈鏄� |
闀峰害 | 35.0姣背 |
瀵害 | 35.0姣背 |
鍖呰楂旀潗鏂� | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰９浠ｇ⒓ | BGA |
鍖呯瓑鍍逛唬纰� | BGA1156,34X34,40 |
鍖呰褰㈢媭 | 寤ｅ牬 |
鍖呰棰ㄦ牸 | 缍�(w菐ng)鏍奸櫍鍒� |
鍒堕�犲晢鍖呰瑾槑 | FBGA-1156 |
鐒￠墰鐙�鎱�(t脿i)/RoHS鐙�鎱�(t脿i) | 鐒￠墰/绗﹀悎RoHS妯欐簴 |
婵曞害鏁忔劅搴︾瓑绱�(MSL) | 4(72灏忔檪) |
?灏堢敤绱氳伅(li谩n)閫ｆ帴
?鍙伕鐨勬祦姘寸窔
?闈堟椿鐨勯厤缃伕闋�
?鎻愰珮浜嗚矾鐢辨晥鐜�
?闆欑鍙AM妯″
?1.2鑷�2.5VI /O鎿嶄綔
?36-Kb濉奟AM/FIFO
?鎻愪緵2500Mb /s鏀寔
?鑷嫊绺界窔瀵害妾㈡脯
?绔粸鍜屾牴绔彛鑳藉
?鍙伕鐨勬寜浣嶉倧杓姛鑳�
?SPI鍜屽苟琛孎lash鎺ュ彛
?40 nm閵匔MOS宸ヨ棟鎶�琛�
?鍏堥�茬殑楂樻�ц兘FPGA閭忚集
?闆橪UT5(5杓稿叆LUT)閬搁爡
?鐪熸鐨�6杓稿叆鏌ユ壘琛�(LUT)鎶�琛�
?LXT鍜孲XT鍣ㄤ欢鍦ㄥ悓涓�灏佽涓吋瀹�
?SRL32 /闆橲RL16锛屽付娉ㄥ唺杓稿嚭閬搁爡
?寮峰ぇ鐨勬贩鍚堟ā寮忔檪閻樼鐞嗗櫒(MMCM)
?鍙法绋嬬殑
銆傞洐绔彛瀵害楂橀仈36浣�
銆傜啊鍠殑闆欑鍙ｅ搴﹂珮閬�72浣�
?澧炲挤鐨勫彲绶ㄧ▼FIFO閭忚集
?鍏�(n猫i)缃彲閬哥殑绯鹃尟闆昏矾
?鍏堥�茬殑DSP48E1鍒囩墖
?鍙伕鎿囧皣姣忓�嬪鐢ㄤ綔鍏╁�嬬崹绔嬬殑18 Kb濉�
?楂樻�ц兘骞惰SelectIO?鎶�琛�
?浣跨敤ChipSync?鎶�琛撻�茶婧愬悓姝ユ帴鍙�
?鏁�(sh霉)瀛楁帶鍒堕樆鎶�(DCI)鏈夋簮绲傜
?闈堟椿鐨勭窗绮掑害I /O閵�琛屾キ(y猫)鍕�
?鏀寔楂橀�熷瓨鍎插櫒鎺ュ彛锛屽叿鏈夐泦鎴愮殑瀵叆鍧囪 鍔熻兘
?25 x 18锛屼簩閫插埗瑁滅⒓涔樻硶鍣�/绱姞鍣�
?鏂扮殑鍙伕闋愬姞娉曞櫒锛屽彲鍗�(xi茅)鍔╅亷婵炬噳鐢ㄧ▼搴�
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?鎵�鏈夎ō鍌欎笂鐨勭郴绲�(t菕ng)鐩�(ji膩n)瑕栧櫒鍔熻兘
?鐗囦笂/鐗囧鐔遍噺鍜岄浕婧愰浕澹撶洠(ji膩n)鎺�
?JTAG瑷晱鎵�鏈夊彈鐩�(ji膩n)鎺х殑鏁�(sh霉)閲�
?鐢ㄤ簬PCIExpress?瑷▓鐨勯泦鎴愭帴鍙ｆā濉�
?绗﹀悎PCI Express Base Specification 2.0
?Gen1(2.5 Gb/s)鍜孏en2(5 Gb/s)鏀寔GTX鏀剁櫦(f膩)鍣�
?姣忓�嬪x1锛寈2锛寈4鎴杧8閫氶亾鏀寔
?GTX鏀剁櫦(f膩)鍣細楂橀仈6.6 Gb/s
?FPGA閭忚集涓殑閬庨噰妯ｆ敮鎸佷綆浜�480 Mb/s鐨勬暩(sh霉)鎿�(j霉)閫熺巼銆�
?GTH鏀剁櫦(f膩)鍣細2.488 Gb/s鑷宠秴閬�11 Gb/s
?闆嗘垚鐨�10/100/1000 Mb/s浠ュお缍�(w菐ng)MAC濉�
?浣跨敤GTX鏀剁櫦(f膩)鍣ㄦ敮鎸�1000BASE-X PCS / PMA鍜孲GMII
?浣跨敤SelectIO鎶�琛撹硣婧愭敮鎸丮II锛孏MII鍜孯GMII
?1.0V鏍稿績闆诲(鍍呴檺-1锛�-2锛�-3閫熷害绛夌礆)
?浣庡姛鑰�0.9V鏍稿績闆诲閬搁爡(鍍呴檺-1L閫熷害绛夌礆)
?LUT /闆欒Ц鐧�(f膩)鍣ㄥ皪鐢ㄤ簬闇�瑕佽睈瀵屽瘎瀛樺櫒娣峰悎鐨勬噳鐢�
?Virtex-6 LXT FPGA锛氬叿鏈夐珮绱氫覆琛岄�ｆ帴鐨勯珮鎬ц兘閭忚集
?姣�6杓稿叆LUT鏈�64浣�(鎴栧叐鍊�32浣�)鍒嗗竷寮廘UT RAM閬搁爡
?楂樹俊铏熷畬鏁存�у�掕鑺墖灏佽锛屾彁渚涙婧栨垨鐒￠墰灏佽閬搁爡
?MMCM妯″鎻愪緵闆跺欢閬茬珐娌�锛岄牷鐜囧悎鎴愶紝鏅傞悩鐩哥Щ锛岃几鍏ユ姈鍕曟烤娉㈠拰鐩镐綅鍖归厤鏅傞悩鍒嗛牷
XC6VLX130T-2FF1156C绗﹁櫉
XC6VLX130T-2FF1156C鑵冲嵃
