鏅傞枔锛�2025/5/12 12:59:31
闁辫畝锛�23
XC6VLX240T-1FF1156C 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-6 绯诲垪 FPGA 鑺墖涓殑涓�鍊嬪瀷铏�銆傝┎绯诲垪 FPGA 閲濆皪楂樻�ц兘瑷堢畻銆佹暩(sh霉)瀛椾俊铏熻檿鐞嗗拰寰╅洔宓屽叆寮忕郴绲�(t菕ng)瑷▓鑰屽劒(y艒u)鍖栵紝寤ｆ硾鎳夌敤浜庨�氫俊銆佽埅绌鸿埅澶�銆佸伐妤�(y猫)鎺у埗浠ュ強閱�(y墨)鐧傝ō鍌欑瓑闋樺煙銆�
銆�銆�Virtex-6 绯诲垪閲囩敤 40nm 鍒剁▼宸ヨ棟锛屽叿鍌欒睈瀵岀殑閭忚集璩囨簮銆侀珮閫熶覆琛屾敹鐧�(f膩)鍣ㄥ拰澶у閲忓瓨鍎插櫒銆俋C6VLX240T 鏄� Virtex-6 LX 鍣ㄤ欢鐨勪竴鍊嬪叿楂斿瀷铏�锛屽叿鏈夐珮瀵嗗害閭忚集鍠厓鍜屽挤澶х殑 I/O 鍔熻兘锛岄仼鍚堥渶瑕佸ぇ閲忛倧杓硣婧愬拰楂樻�ц兘鐨勬噳鐢ㄥ牬鏅�銆�
鍣ㄤ欢椤炲瀷锛欶PGA
銆�銆�绯诲垪锛歏irtex-6
銆�銆�鍨嬭櫉锛歑C6VLX240T-1FF1156C
銆�銆�灏佽锛欶FG1156
銆�銆�閫熷害绛夌礆锛�-1
銆�銆�閰嶇疆闁冨瓨锛氫笉闆嗘垚
銆�銆�閭忚集鍠厓鏁�(sh霉)锛氱磩 240,000
銆�銆�DSP Slice 鏁�(sh霉)閲忥細1,140
銆�銆�Block RAM 瀹归噺锛氱磩 13.8Mb
銆�銆�灏堢敤鏅傞悩璩囨簮锛氬閬� 16 鍊嬪叏灞�鏅傞悩
銆�銆�楂橀�熶覆琛屾敹鐧�(f膩)鍣ㄦ暩(sh霉)閲忥細24 鍊�
銆�銆�鏈�澶у伐浣滈牷鐜囷細楂橀仈 550 MHz
銆�銆�I/O 寮曡叧鏁�(sh霉)锛氭渶澶� 840
銆�銆�鍔熻�楄寖鍦嶏細鏍规摎(j霉)鎳夌敤涓嶅悓锛屽吀鍨嬪嫊鎱�(t脿i)鍔熻�楃磩鐐� 10W 鑷� 20W
XC6VLX240T-1FF1156C 鎻愪緵浜嗛潪甯搁珮鐨勯倧杓瘑搴﹀拰闈堟椿鐨� I/O 閰嶇疆鑳藉姏銆傚叾涓昏鐗规�у寘鎷細
銆�銆�1. 楂樻�ц兘鏋舵锛氬熀浜� Virtex-6 鐨勫彲绶ㄧ▼閭忚集鏋舵鏀寔寰╅洔鐨勭畻娉曞鐝�(xi脿n)鍜岄珮鏁堢殑鏁�(sh霉)鎿�(j霉)鍚炲悙銆�
銆�銆�2. 楂橀�熶覆琛屾敹鐧�(f膩)鍣細鏀寔閫熺巼楂橀仈 6.6Gbps 鐨勯珮閫熶覆琛岄張璺�锛岄仼鐢ㄤ簬鑳屾澘閫氫俊鍜屽厜绾栨帴鍙�銆�
銆�銆�3. 澶у閲� Block RAM 鍜� DSP Slice锛氭彁渚涗簡璞愬瘜鐨勫収閮ㄥ瓨鍎茶硣婧愬拰灏堢敤鏁�(sh霉)瀛椾俊铏熻檿鐞嗗柈鍏冿紝閬╁悎寰╅洔鐨勬暩(sh霉)瀛搁亱绠椾换鍕�銆�
銆�銆�4. 鏀寔澶氱ó閰嶇疆妯″紡锛氬寘鎷富寰� SPI Flash銆侀倞鐣屾巸鎻� JTAG 鍜屼覆琛屽瑷帴鍙ｇ瓑閰嶇疆鏂瑰紡銆�
銆�銆�5. 鍙潬鎬у寮峰姛鑳斤細闆嗘垚浜嗛尟瑾ゆ娓垏绯炬姗熷埗锛圗CC锛�锛屾彁楂樹簡闂滈嵉鎳夌敤涓殑鏁�(sh霉)鎿�(j霉)瀹屾暣鎬�銆�
銆�銆�6. 浣庡姛鑰楀劒(y艒u)鍖栵細閫氶亷鍕曟厠(t脿i)闆绘簮绠＄悊鎶�琛撻檷浣庢暣楂旈亱琛屽姛鑰�锛屽悓鏅傜董鎸侀珮鎬ц兘琛ㄧ従(xi脿n)銆�
XC6VLX240T-1FF1156C 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 閫氫俊瑷倷锛氬鐒＄窔鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙涓殑鏁�(sh霉)鎿�(j霉)鍖呰檿鐞嗘ā濉�銆�
銆�銆�2. 鍦栧儚铏曠悊锛氬寘鎷啱(y墨)鐧傛垚鍍忕郴绲�(t菕ng)銆佽闋荤法纰艰В纰煎櫒浠ュ強瀵︽檪鍦栧儚鍒嗘瀽骞宠嚭銆�
銆�銆�3. 宸ユキ(y猫)鑷嫊鍖栵細渚嬪閬嬪嫊鎺у埗鍣�銆佹鍣ㄤ汉鎺у埗绯荤当(t菕ng)鍜屽伐寤犳暩(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)銆�
銆�銆�4. 鑸┖鑸ぉ鑸囧湅闃诧細娑夊強闆烽仈淇¤櫉铏曠悊銆佽(w猫i)鏄熼�氫俊杓夎嵎鍜屽叾浠栭珮鍙潬鎬ч渶姹傜殑鍫村悎銆�
銆�銆�5. 娓│娓噺鍎�鍣細鐢ㄤ簬绀烘尝鍣�銆侀牷璀滃垎鏋愬剙绛夐珮绔脯瑭﹁ō鍌欑殑鏍稿績鏁�(sh霉)鎿�(j霉)铏曠悊閮ㄥ垎銆�
XC6VLX240T-2FF1156C
銆�銆�XC6VL1156C
