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XC6VLX365T-1FF1759I鏄疿ilinx鍏徃鎺ㄥ嚭鐨刅irtex-6绯诲垪FPGA鑺墖涓殑涓�鍊嬪瀷铏�銆傝┎绯诲垪鍣ㄤ欢閲囩敤40nm宸ヨ棟鍒堕�狅紝鎻愪緵楂樻�ц兘銆佷綆鍔熻�楀拰楂橀倧杓瘑搴︾殑瑙ｆ焙鏂规銆俋C6VLX365T灞簬Virtex-6 LX绯诲垪锛屼富瑕侀潰鍚戦珮绔暩(sh霉)瀛椾俊铏熻檿鐞嗗拰寰╅洔鎺у埗閭忚集鐨勬噳鐢ㄥ牬鏅��
銆�銆�Virtex-6 FPGA瀹舵棌鎻愪緵浜嗚睈瀵岀殑鍔熻兘妯″锛屽寘鎷珼SP Slice銆丅lock RAM銆侀珮閫熶覆琛屾敹鐧�(f膩)鍣ㄧ瓑锛屽彲婊胯冻閫氫俊銆佸唬鎾�佽粛浜�銆佸伐妤�(y猫)绛夊绋牁鍩熺殑闇�姹�銆傛鍏烽珨鍨嬭櫉甯舵湁1759鍊嬪紩鑵�锛屽皝瑁濆舰寮忕偤FFG1759锛屽苟鍏锋湁-1閫熷害绛夌礆锛岀⒑淇濅簡鍏跺湪楂橀牷宸ヤ綔鐠�(hu谩n)澧冧笅鐨勬�ц兘琛ㄧ従(xi脿n)銆�
鍨嬭櫉锛歑C6VLX365T-1FF1759I
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛歏irtex-6 LX
銆�銆�宸ヨ棟锛�40nm
銆�銆�FPGA瑕�(gu墨)妯★細365K閭忚集鍠厓
銆�銆�RAM瀹归噺锛�21.3Mb
銆�銆�DSP Slice鏁�(sh霉)閲忥細960鍊�
銆�銆�閰嶇疆闁冨瓨锛氫笉鍏�(n猫i)缃�
銆�銆�I/O Bank闆诲鑼冨湇锛�1.8V/2.5V/3.3V
銆�銆�鏍稿績闆诲锛�1.0V
銆�銆�灏佽锛欶FG1759
銆�銆�閫熷害绛夌礆锛�-1
XC6VLX365T-1FF1759I鍏峰倷浠ヤ笅椤憲鐗规�э細
銆�銆�1. 楂橀倧杓瘑搴︼細365K閭忚集鍠厓浣垮叾鑳藉鏀寔寰╅洔鐨勬暩(sh霉)瀛楅浕璺ō瑷�銆�
銆�銆�2. DSP Slice锛氬寘鍚�960鍊嬪皥鐢―SP Slice锛屽彲鐢ㄤ簬楂樻晥瀵︾従(xi脿n)娴粸閬嬬畻銆佹烤娉㈠櫒瑷▓浠ュ強鍏朵粬鏁�(sh霉)瀛稿瘑闆嗗瀷浠诲嫏銆�
銆�銆�3. 鍏�(n猫i)缃瓨鍎茶硣婧愶細21.3Mb鐨凚lock RAM鍙互鐢ㄤ簬鏁�(sh霉)鎿�(j霉)绶╂矕銆佹煡鎵捐〃绛夊姛鑳�銆�
銆�銆�4. 楂橀�熶覆琛屾敹鐧�(f膩)鍣細鏀寔楂橀仈6.6Gbps鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼锛岄仼鐢ㄤ簬鍏夌簴閫氫俊鍜岃儗鏉夸簰鑱�(li谩n)銆�
銆�銆�5. 澶氱ó鎺ュ彛妯欐簴鏀寔锛氬PCIe銆丼ATA銆佸崈鍏嗕互澶恫(w菐ng)绛夊崝(xi茅)璀�銆�
銆�銆�6. 鍔熻�楃鐞嗭細閫氶亷鏅傞悩闁�鎺у拰鍕曟厠(t脿i)闆绘簮瑾跨瘈(ji茅)鎶�琛撻檷浣庢暣楂斿姛鑰椼��
銆�銆�7. 鍙潬鎬ч珮锛氱稉(j墨ng)閬庡毚鏍兼脯瑭�锛岄仼鍚堣埅绌鸿埅澶�銆侀啱(y墨)鐧傝ō鍌欑瓑灏嶅彲闈犳�ц姹傛サ楂樼殑闋樺煙銆�
XC6VLX365T-1FF1759I寤ｆ硾鎳夌敤浜庝互涓嬪咕鍊嬮牁鍩燂細
銆�銆�1. 閫氫俊绯荤当(t菕ng)锛氬寘鎷熀绔�銆佽矾鐢卞櫒銆佷氦鎻涙绛夎ō鍌欎腑鐨勪俊铏熻檿鐞嗚垏鍗�(xi茅)璀拌В鏋愩��
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銆�銆�3. 宸ユキ(y猫)鑷嫊鍖栵細閬嬪嫊鎺у埗銆佹鍣ㄨ瑕恒�佹暩(sh霉)鎿�(j霉)閲囬泦鑸囩洠(ji膩n)鎺�銆�
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銆�銆�5. 鑸┖鑸ぉ锛氬皫鑸郴绲�(t菕ng)銆侀浄閬斾俊铏熻檿鐞嗙瓑闂滈嵉浠诲嫏銆�
銆�銆�6. 娓│娓噺锛氱ず娉㈠櫒銆侀牷璀滃垎鏋愬剙绛夐珮鎬ц兘鍎�鍣ㄤ腑鐨勬暩(sh霉)鎿�(j霉)閲囬泦鑸囧垎鏋�銆�
銆�銆�姝よ姱鐗囨啈鍊熷叾寮峰ぇ鐨勬�ц兘鍜岄潏娲绘��锛屽湪闇�瑕佸揩閫熷師鍨嬮璀夋垨瀹氬埗纭欢鏋舵鐨勫牬鍚堝挨鐐洪仼鐢�銆�
XC6VLX365T-2FF1759I
銆�銆�XC6VLX365T-3FF1759I
