鍨嬭櫉锛歑C7A15T-1CSG324I
銆�銆�鍝佺墝锛歑ilinx
銆�銆�灏佽�濓細CSG324
銆�銆�宸ヨ棟锛�28nm
銆�銆�FPGA 绯诲垪锛欰rtix-7
銆�銆�閭忚集鍠�鍏冩��(sh霉)閲忥細15,000
銆�銆�RAM 瀹归噺锛�491 Kb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細40
銆�銆�閰嶇疆妯″紡锛歋electMAP 鍜� JTAG
銆�銆�I/O 寮曡叧鏁�(sh霉)锛�236
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��-40掳C 鑷� +100掳C
銆�銆�渚涢浕闆诲�擄細鏍稿績闆诲�� 1.0V锛孖/O 闆诲�� 1.8V/2.5V/3.3V

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XC7A15T-1CSG324I 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 閫氫俊瑷�(sh猫)鍌欙細濡傜劇绶氬熀绔欍�佸皬鍨嬭渹绐╃恫(w菐ng)绲�(lu貌)銆佽矾鐢卞櫒鍜屼氦鎻涙�熶腑鐨勪俊铏熻檿鐞嗘ā濉娿��
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XC7A15T-1FTG256I
銆�銆�XC7A15T-1CSG324C
銆�銆�XC7A15T-2CSG324I