鏅傞枔锛�2025/5/16 19:03:25
闁辫畝锛�26
XC7A200T-L3FBG676E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Artix-7 绯诲垪 FPGA 鑺墖涔嬩竴锛屽爆浜庨珮绔瀷铏熴�侫rtix-7 绯诲垪涓昏閲濆皪浣庢垚鏈�銆佷綆鍔熻�楁噳鐢ㄩ�茶浜嗗劒(y艒u)鍖�锛屽悓鏅傛彁渚涗簡寮峰ぇ鐨勬�ц兘鍜岄潏娲绘�с�傝┎鑺墖閲囩敤 28nm 宸ヨ棟鍒堕��锛屽叿鏈夎睈瀵岀殑閭忚集璩囨簮銆丏SP 妯″銆丅RAM 鍜岄珮閫熶覆琛屾敹鐧�(f膩)鍣ㄧ瓑鐗规��锛屽唬娉涙噳鐢ㄤ簬閫氫俊銆佸伐妤�(y猫)鎺у埗銆侀啱(y墨)鐧傛垚鍍忋�佸唬鎾闋荤瓑闋樺煙銆�
銆�銆�XC7A200T-L3FBG676E 涓殑 -L3 琛ㄧず閫熷害绛夌礆锛孎(xi脿n)BG676 琛ㄧず灏佽椤炲瀷鐐� Fine Pitch BGA 灏佽锛屽紩鑵虫暩(sh霉)鐐� 676銆�
閭忚集鍠厓锛�205,920
銆�銆�DSP48E1 妯″锛�480
銆�銆�Block RAM锛�1,140 Kb
銆�銆�灏堢敤 IO 寮曡叧锛�316
銆�銆�閰嶇疆闁冨瓨鏀寔锛氬惁
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�闆绘簮闆诲锛�1.0V 鏍稿績闆诲锛�1.8V 杓斿姪闆诲
銆�銆�灏佽锛欶BG676
XC7A200T-L3FBG676E 鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樺瘑搴﹂倧杓硣婧愶紝閬╁悎寰╅洔绠楁硶瀵︾従(xi脿n)鍜屾暩(sh霉)鎿�(j霉)铏曠悊浠诲嫏銆�
銆�銆�2. 鍏х疆 DSP48E1 妯″锛岃兘澶犻珮鏁堥�茶娴粸閬嬬畻鍜屾暩(sh霉)瀛椾俊铏熻檿鐞�銆�
銆�銆�3. 鏀寔楂橀仈 1.25Gbps 鐨� GTH 鏀剁櫦(f膩)鍣�锛岄仼鐢ㄤ簬楂橀�熼�氫俊鎺ュ彛銆�
銆�銆�4. 鎻愪緵澶氱ó鏅傞悩绠＄悊閬搁爡锛屼緥濡� PLL 鍜� MMCM锛岀⒑淇濈簿纰虹殑鏅傞悩鍒嗛厤銆�
銆�銆�5. 鍏х疆 PCIe 纭牳妯″锛岀啊鍖栦簡鑸囦富姗熺郴绲�(t菕ng)鐨勯�ｆ帴瑷▓銆�
銆�銆�6. 鍔熻�楀劒(y艒u)鍖栬ō瑷�锛岄仼鍚堝皪鍔熻�楁晱鎰熺殑鎳夌敤鍫存櫙銆�
銆�銆�7. 鏀寔閮ㄥ垎閲嶆柊閰嶇疆鍔熻兘锛屽厑瑷卞嫊鎱�(t脿i)鏇存柊閮ㄥ垎闆昏矾鑰岀劇闇�閲嶅暉鏁村�嬬郴绲�(t菕ng)銆�
銆�銆�8. 鍊熷姪 Vivado Design Suite 闁嬬櫦(f膩)宸ュ叿锛屽彲浠ュ揩閫熷畬鎴愯ō瑷堣几鍏�銆佺稖鍚�銆佸竷灞�甯冪窔浠ュ強椹楄瓑銆�
瑭插瀷铏熺殑 FPGA 涓昏鐢ㄤ簬浠ヤ笅闋樺煙锛�
銆�銆�1. 閫氫俊瑷倷锛氬鍩虹珯銆佽矾鐢卞櫒銆佷氦鎻涙涓殑鍗�(xi茅)璀拌綁鎻涘拰鏁�(sh霉)鎿�(j霉)鍖呰檿鐞嗐��
銆�銆�2. 宸ユキ(y猫)鑷嫊鍖栵細瀵︽檪鎺у埗銆侀亱鍕曟帶鍒跺拰楂樼簿搴︽脯閲忕郴绲�(t菕ng)銆�
銆�銆�3. 閱�(y墨)鐧傛垚鍍忥細CT 鎺冩弿鍎�銆佽秴鑱叉尝瑷倷鐨勬暩(sh霉)鎿�(j霉)閲囬泦鑸囧湒鍍忛噸寤恒��
銆�銆�4. 寤ｆ挱瑕栭牷锛氶珮娓�/4K 瑕栭牷绶ㄧ⒓瑙ｇ⒓銆佸箑鍚屾鍜岀壒鏁堢敓鎴�銆�
銆�銆�5. 娓│娓噺鍎�鍣細浠绘剰娉㈠舰鐧�(f膩)鐢熷櫒銆佺ず娉㈠櫒绛夐珮鎬ц兘娓│瑷倷銆�
銆�銆�6. 瀹夐槻鐩�(ji膩n)鎺э細瑕栭牷娴佸垎鏋愩�佹櫤鑳借瓨鍒ョ瓑鍔熻兘鐨勫祵鍏ュ紡骞宠嚭銆�
銆�銆�7. 绉戝瑷堢畻锛氱煩闄ｉ亱绠椼�佺缍撶恫(w菐ng)绲¤〒绶存帹鐞嗙瓑楂樻�ц兘瑷堢畻浠诲嫏銆�
XC7A200T-2FBG676E, XC7A200T-3FBG676C
