鏅傞枔锛�2025/4/30 17:58:05
闁辫畝锛�32
XC7A50T-2FG484C 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Artix-7 绯诲垪 FPGA 鑺墖涓殑涓�鍊嬪瀷铏�銆侫rtix-7 绯诲垪 FPGA 闈㈠悜浣庡姛鑰楀拰楂樻�у児姣旂殑鎳夌敤鍫存櫙锛岄仼鍚堟秷璨婚浕瀛�銆侀�氫俊鍩虹瑷柦銆佸伐妤�(y猫)鑷嫊鍖栫瓑闋�(l菒ng)鍩�銆傝┎鑺墖閲囩敤 28nm 鍒剁▼宸ヨ棟鍒堕��锛屽叿鍌欒睈瀵岀殑閭忚集璩囨簮銆丏SP 妯″浠ュ強楂橀�熸敹鐧�(f膩)鍣紝鑳藉婊胯冻澶氱ó寰╅洔瑷▓闇�姹�銆�
銆�銆�XC7A50T 鏄� Artix-7 绯诲垪涓叿鏈変腑绛夎(gu墨)妯￠倧杓硣婧愮殑鍨嬭櫉锛屽叾灏佽褰㈠紡鐐� FG484锛團lip-Chip BGA 484 寮曡叧锛�锛�-2 琛ㄧず閫熷害绛夌礆锛岃�� C 琛ㄧず鍟嗘キ(y猫)绱氭韩搴﹁寖鍦嶏紙0掳C 鑷� +85掳C锛�銆�
鍣ㄤ欢绯诲垪锛欰rtix-7
銆�銆�鍨嬭櫉锛歑C7A50T
銆�銆�灏佽锛欶G484
銆�銆�閫熷害绛夌礆锛�-2
銆�銆�婧害鑼冨湇锛�0掳C 鑷� +85掳C
銆�銆�閭忚集鍠厓鏁�(sh霉)锛氱磩 50,000 鍊�
銆�銆�鏌ユ壘琛紙LUT锛夛細绱� 30,100 鍊�
銆�銆�瑙哥櫦(f膩)鍣細绱� 60,200 鍊�
銆�銆�BRAM锛氱磩 1.2 Mb
銆�銆�DSP Slice锛氱磩 120 鍊�
銆�銆�鐢ㄦ埗 I/O 鏁�(sh霉)閲忥細鏈�澶� 354 鍊�
銆�銆�閰嶇疆妯″紡锛歋electMAP銆丼lave Serial銆丮aster SPI銆丅oundary Scan
銆�銆�宸ヤ綔闆诲锛氭牳蹇冮浕澹撶偤 1.0V锛孖/O 闆诲鏀寔 1.8V銆�2.5V 鍜� 3.3V
XC7A50T-2FG484C 鎻愪緵浜嗗挤澶х殑鎬ц兘鍜岄潏娲绘��锛岄仼鐢ㄤ簬澶氱ó鎳夌敤闋�(l菒ng)鍩�銆�
銆�銆�1. 楂橀泦鎴愬害锛氳姱鐗囧収(n猫i)閮ㄩ泦鎴愪簡澶ч噺鐨勯倧杓硣婧愬拰 DSP 妯″锛屽彲瀵︾従(xi脿n)寰╅洔鐨勬暩(sh霉)瀛椾俊铏熻檿鐞嗗姛鑳�銆�
銆�銆�2. 浣庡姛鑰楄ō瑷堬細Artix-7 绯诲垪閲囩敤鍎�(y艒u)鍖栫殑 28nm 宸ヨ棟锛岃兘澶犲湪淇濊瓑鎬ц兘鐨勫悓鏅傞’钁楅檷浣庡姛鑰�銆�
銆�銆�3. 楂橀�熸帴鍙ｆ敮鎸侊細鏀寔 PCIe銆佸崈鍏嗕互澶恫(w菐ng)銆丏DR3/DDR4 鍏�(n猫i)瀛樻帶鍒跺櫒绛夊绋珮閫熸帴鍙ｅ崝(xi茅)璀�銆�
銆�銆�4. 鍙法绋嬫�э細鐢ㄦ埗鍙互閫氶亷纭欢鎻忚堪瑾炶█锛堝 Verilog 鎴� VHDL锛夊皪 FPGA 閫茶绶ㄧ▼锛岄潏娲婚仼鎳変笉鍚岀殑鎳夌敤鍫存櫙銆�
銆�銆�5. 瀹夊叏鐗规�э細鎻愪緵鍔犲瘑閰嶇疆浣嶆祦鍜屽畨鍏ㄥ暉鍕曞姛鑳斤紝淇濊鐭ヨ瓨鐢�(ch菐n)娆�(qu谩n)鍜岀郴绲�(t菕ng)瀹夊叏銆�
銆�銆�6. 鏄撲簬闁嬬櫦(f膩)锛歑ilinx 鎻愪緵浜� Vivado Design Suite 闁嬬櫦(f膩)宸ュ叿锛屾敮鎸佸緸瑷▓杓稿叆鍒伴璀夌殑鍏ㄦ祦绋嬮枊鐧�(f膩)銆�
XC7A50T-2FG484C 寤ｆ硾鎳夌敤浜庝互涓嬮牁(l菒ng)鍩燂細
銆�銆�1. 閫氫俊瑷倷锛氬灏忓瀷鍩虹珯銆佺劇绶氭帴鍏ラ粸銆佹暩(sh霉)鎿�(j霉)鍌宠几妯″绛�銆�
銆�銆�2. 瑕栭牷铏曠悊锛氳闋荤法瑙ｇ⒓銆佸湒鍍忓寮枫�佸鏅傝闋诲垎鏋�銆�
銆�銆�3. 宸ユキ(y猫)鎺у埗锛氶亱鍕曟帶鍒�銆佸伐寤犺嚜鍕曞寲銆佹鍣ㄤ汉銆�
銆�銆�4. 閱�(y墨)鐧傝ō鍌欙細閱�(y墨)瀛告垚鍍�銆佹偅鑰呯洠(ji膩n)璀风郴绲�(t菕ng)銆�
銆�銆�5. 娑堣不椤為浕瀛愮敘(ch菐n)鍝侊細楂樻竻椤ず椹�(q奴)鍕�銆侀煶闋昏檿鐞�銆�
銆�銆�6. 宓屽叆寮忚▓绠楋細楂樻�ц兘宓屽叆寮忚檿鐞嗗櫒鍔犻�熷钩鑷�銆�
XC7A50T-2FTG256C
銆�銆�XC7A50T-2CSG324C
銆�銆�XC7A50T-2FBG484C
